Data compression device and method using floating point format

1. A data compression device comprising:

an analog to digital converter (ADC) configured to convert an analog signal into a digital signal including in-phase and quadrature components; and

a compressor configured to:

generate a 28-bit fixed-point digital signal in which bits of the in-phase and quadrature components are alternately arranged;

generate an exponent bit string by comparing n most significant bits of a data bit string excluding two sign bits in the 28-bit fixed-point digital signal with preset mapping data, wherein the exponent bit string includes 4 bits;

generate a mantissa bit string composed of 14 bits corresponding to up to 14th bit from a bit next to the n most significant bits of the data bit string; and

generate a 20-bit floating point digital signal by combining the two sign bits, the exponent bit string, and the mantissa bit string,

wherein n is a natural number equal to or greater than 2 and equal to or less than 12.

2. The data compression device of claim 1 , wherein,

if there is no mapping bit string corresponding to the n most significant bits in the mapping data, the compressor is configured to determine whether there are mapping bit string corresponding to n+1 most significant bits and generate the exponent bit string.

3. The data compression device of claim 1 , wherein

the mapping data includes two mapping bit strings corresponding to two bits.

4. The data compression device of claim 1 , wherein

the mapping data includes two mapping bit strings corresponding to three bits.

5. The data compression device of claim 1 , wherein

the mapping data includes two mapping bit strings corresponding to four bits.

6. The data compression device of claim 1 , wherein

the mapping data includes three mapping bit strings corresponding to five bits.

7. A data decompression device comprising:

a decompressor configured to:

receive a 20-bit floating point digital signal composed of two sign bits, a 4-bit exponent bit string, and a 14-bit mantissa bit string;

generate n most significant bits by comparing the 4-bit exponent bit string with preset mapping data; and

generate and output a 28-bit fixed-point digital signal in which bits of in-phase and quadrature components are alternately arranged by combining the two sign bits, the 14-bit mantissa bit string and the n most significant bits; and

a digital to analog converter (DAC) configured to convert the 28-bit fixed-point digital signal into an analog signal,

wherein n is a natural number equal to or greater than 2 and equal to or less than 12.

8. The data decompression device of claim 7 , wherein

the mapping data includes two mapping bit strings corresponding to two bits.

9. The data decompression device of claim 7 , wherein

the mapping data includes two mapping bit strings corresponding to three bits.

10. The data decompression device of claim 7 , wherein

the mapping data includes two mapping bit strings corresponding to four bits.

11. The data decompression device of claim 7 , wherein

the mapping data includes three mapping bit strings corresponding to five bits.

12. The data decompression device of claim 7 , wherein,

when a value obtained by combining the two sign bits, the 14-bit mantissa bit string, and the n most significant bits is less than 28 bits, the decompressor is configured to generate a lost bit string corresponding to a number of insufficient bits, and generate the 28-bit fixed-point digital signal by combining the two sign bits, the n most significant bits, the 14-bit mantissa bit string, and the lost bit string,

wherein a most significant bit of the in-phase component or the quadrature component constituting the lost bit string corresponds to HIGH.

13. The data decompression device of claim 12 , wherein up to a least significant bit from a next most significant bit each of the in-phase and quadrature components constituting the lost bit string correspond to LOW.