Far end crosstalk cancellation for serdes links
View Patent ↗A serializer-deserializer (SerDes) integrated circuit (IC) chip includes a first SerDes receiver circuit having a first input for coupling to a first SerDes link, and a first output. A second SerDes receiver circuit has a second input for coupling to a second SerDes link. The second SerDes receiver circuit includes a second output. Crosstalk filter circuitry is disposed between the first SerDes receiver circuit and the second SerDes receiver circuit.
1. A serializer-deserializer (SerDes) integrated circuit (IC) chip comprising:
a first SerDes receiver circuit having a first input for coupling to a first SerDes link, the first SerDes receiver circuit including a first analog-to-digital (ADC) converter having a first analog input and a first digital output;
a second SerDes receiver circuit having a second input for coupling to a second SerDes link, the second SerDes receiver circuit including a second analog-to-digital (ADC) converter having a second analog input and a second digital output; and
crosstalk filter circuitry configured in a feed-forward architecture and disposed between the first SerDes receiver circuit and the second SerDes receiver circuit, wherein the crosstalk filter circuitry includes
a first summing circuit to receive a version of the output from the first ADC,
a second summing circuit to receive a version of the output from the second ADC,
a first crosstalk filter coupling the output of the first ADC to the second summing circuit, and
a second crosstalk filter coupling the output of the second ADC to the first summing circuit.
2. The SerDes IC chip according to claim 1 , wherein the first crosstalk filter and the second crosstalk filter are in the form of adaptive finite impulse response (FIR) filters.
3. The SerDes IC chip according to claim 1 , further comprising:
first equalization circuitry disposed between the output of the first ADC and the first summing circuit; and
second equalization circuitry disposed between the output of the second ADC and the second summing circuit.
4. A serializer-deserializer (SerDes) integrated circuit (IC) chip comprising:
a first SerDes receiver circuit having a first input for coupling to a first SerDes link, the first SerDes receiver circuit including a first summing circuit having a first output, and a first slicer circuit having a first input coupled to the first output and a first slicer output;
a second SerDes receiver circuit having a second input for coupling to a second SerDes link, the second SerDes receiver circuit includes a second summing circuit having a second output, and a second slicer circuit having a second input coupled to the second output, the second slicer circuit having a second slicer output; and
crosstalk filter circuitry configured in a feedback architecture and disposed between the first SerDes receiver circuit and the second SerDes receiver circuit wherein the crosstalk filter circuitry includes
a first crosstalk filter configured to feed back the output of the first slicer to the second summing circuit, and
a second crosstalk filter configured to feed back the output of the second slicer to the first summing circuit.
5. The SerDes IC chip according to claim 4 , wherein the first crosstalk filter and the second crosstalk filter are in the form of adaptive finite impulse response (FIR) filters.
6. The SerDes IC chip according to claim 4 , further comprising:
first equalization circuitry disposed between the output of the first slicer and the first summing circuit; and
second equalization circuitry disposed between the output of the second slicer and the second summing circuit.
7. The SerDes IC chip according to claim 6 , wherein the first equalization circuitry and the second equalization circuitry comprise decision-feedback equalizer (DFE) circuits.
8. A serializer-deserializer (SerDes) integrated circuit (IC) chip comprising:
a first SerDes transmit circuit having a first transmit output for coupling to a first SerDes link, the first SerDes transmit circuit including a first data input and a first summing circuit having a first input and a first output;
a second SerDes transmit circuit having a second transmit output for coupling to a second SerDes link, the second SerDes transmit circuit including a second data input and a second summing circuit having a second input and a second output; and
crosstalk filter circuitry configured in a feed-forward architecture and disposed between the first SerDes transmit circuit and the second SerDes transmit circuit, wherein the crosstalk filter circuitry includes
a first crosstalk filter configured to feed the input of the first transmit circuit to the second summing circuit, and
a second crosstalk filter configured to feed the input of the second transmit circuit to the first summing circuit.
9. The SerDes IC chip according to claim 8 , wherein the first crosstalk filter and the second crosstalk filter are in the form of adaptive finite impulse response (FIR) filters.
10. The SerDes IC chip according to claim 8 , further comprising:
first equalization circuitry disposed between the input of the first transmit circuit and the first summing circuit; and
second equalization circuitry disposed between the input of the second transmit circuit and the second summing circuit.
11. The SerDes IC chip according to claim 10 , wherein the first equalization circuitry and the second equalization circuitry comprise precoder circuits.