Multi-loop PLL structure for generating an accurate and stable frequency over a wide range of frequencies
A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R 1 ) and a third (N 1 ) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: F out =( N 1/ R 1+ . . . + Nn/Rn )* F cro where N 1 and R 1 are the dividing values of the first auxiliary loop and Ni and Ri with i=2 . . . n−1 being the dividing ratios of any possible further auxiliary loop; and Fcro is the frequency generated by VCO, whereby the multiloop circuit is configured with dividing values which optimizes a cost function F.
1. A multiloop phase locked loop (PLL) circuit comprising, in combination:
a first phase locked loop (PLL) loop comprising:
a first voltage controlled oscillator ( 200 , 300 , 400 ) for generating a first signal having a first frequency (Fcro);
a first phase detector ( 201 , 301 , 401 ) having first and second inputs, said first input receiving a reference frequency (Fref) and said second input receiving the output of a first programmable divider ( 203 , 303 , 403 );
said first programmable divider ( 203 , 303 , 403 ) receiving said first signal;
a first loop filter ( 202 , 302 , 402 ) connected between said first phase detector and said first voltage controlled oscillator;
a second phase locked loop (PLL) comprising:
a second voltage controlled oscillator ( 210 , 310 , 410 ) generating a second signal having a second frequency (F 1 );
a second phase detector ( 211 , 311 , 411 ) having first and second inputs, said first input receiving a signal generated by a second programmable divider ( 214 , 314 , 414 , R 1 ) and said second input receiving the output of a third programmable divider ( 213 , 313 , 413 , N 1 ), wherein said second programmable divider ( 214 , 314 , 414 , R 1 ) and said third programmable divider ( 313 , 313 , 413 , N 1 ) are configured for respectively storing a first variable dividing ratio (R 1 ) and a second variable dividing ratio (N 1 );
said second programmable divider ( 214 , 314 , 414 , R 1 ) having an input receiving said first signal;
said third programmable divider ( 213 , 313 , 413 , N 1 ) having an input receiving said second signal;
a second loop filter ( 212 , 312 , 412 ) having an input receiving the output of said second phase detector ( 211 , 311 , 411 ) and an output connected to an input of said second voltage controlled oscillator ( 210 , 310 , 410 );
a third phase locked loop (PLL) comprising:
a third voltage controlled oscillator ( 220 , 320 , 420 ) for generating a third signal having a third frequency (F 2 );
a third phase detector ( 221 , 321 , 421 ) having first and second inputs, said first input receiving a signal generated by a fourth programmable divider ( 224 , 324 , 424 , R 2 ) and said second input receiving the output of a fifth programmable divider ( 223 , 323 , 423 , N 2 ); wherein said fourth programmable divider ( 224 , 324 , 424 , R 2 ) and said fifth programmable divider ( 223 , 323 , 423 , N 2 ) are configured for respectively storing a third variable dividing ratio (R 2 ) and a fourth variable dividing ration (N 2 );
said fourth programmable divider ( 224 , 324 , 494 424 , R 2 ) having an input receiving said first signal;
said fifth programmable divider ( 223 , 323 , 423 , N 2 ) having an input receiving the output of a first low pass filter ( 225 , 325 , 425 );
said first low pass filter ( 225 , 325 , 425 ) having an input connected to the output of a first mixer ( 219 , 319 );
said mixer (( 219 , 319 , 419 ) having two inputs respectively receiving said second and said third signals;
a third loop filter ( 222 , 322 , 422 ) having an input receiving the output of said third phase detector ( 221 , 321 , 421 ) and an output connected to an input said third voltage controlled oscillator ( 220 , 320 , 420 ); whereby said third signal has a frequency (F 2 ) generated in accordance with the relation:
F 2 =( N 1/ R 1+ . . . + N 2/ R 2)* Fcro
wherein said first, second third and fourth programmable dividers are configured with variable dividing ratios selected to optimize one of the following:
a reduction of the range of one given ratio R 1 /N 1 or R 2 /N 2 ;
a reduction of the range of frequencies used by one among said first, said second and said third multi-loop phase locked loop (PLL) circuits; and
a reduction of spurs impact created by said first, said second and said third voltage controlled oscillators.
2. The multiloop phase locked loop (PLL) circuit according to claim 1 , further comprising:
a fourth phase locked loop (PLL) comprising:
a fourth voltage controlled oscillator ( 330 ) for generating a fourth signal having a fourth frequency (Fout);
a fourth phase detector ( 331 ) having first and second inputs, said first input receiving a signal generated by a sixth programmable divider ( 334 , R 3 ) and said second input receiving an output of a seventh programmable divider ( 333 , N 3 ), wherein said sixth programmable divider ( 334 , R 3 ) and said seventh programmable divider ( 333 , N 3 ) are configured for respectively storing a fifth variable dividing ratio (R 3 ) and a sixth variable dividing ratio (N 3 );
said sixth programmable divider ( 334 , R 3 ) having an input receiving said first signal;
said seventh programmable divider ( 333 , N 3 ) having an input receiving the output of a second low pass filter ( 335 );
said second low pass filter ( 335 ) having an input connected to the output of a second mixer ( 329 );
said second mixer ( 329 ) having two inputs respectively receiving said third signal (F 2 ) and said fourth signal (Fout);
a fourth loop filter ( 332 ) having an input receiving the output of said fourth phase detector ( 334 ) and an output connected to an input of said fourth voltage controlled oscillator ( 330 );
wherein said fourth signal has a frequency (Fout) which is generated in accordance with the relation:
F out =( N 1/ R 1+ N 2/ R 2+ N 3/ R 3)* F cro
wherein said first, second third, fourth, fifth and sixth programmable dividers are configured with variable dividing ratios selected to optimize one of the following:
a reduction of the range of one given ratio R 1 /N 1 or R 2 /N 2 or R 3 /N 3 ;
a reduction of the range of frequencies used by one among said first, said second, said third and said fourth multi-loop phase locked loop (PLL) circuit;
a reduction of spurs impact created by said first, said second, said third and said fourth voltage controlled oscillators.
3. The multiloop phase locked loop (PLL) circuit according to claim 2 , further comprising additional N th phase locked loops (PLL) receiving in parallel said first signal (Fcro) at divide input ( 494 ) and previous PLL output (Fn−1) at mixer input ( 499 ) and generating an output signal
F out =( N 1/ R 1+ N 2/ R 2+ . . . + Nn/Rn )* F cro
where Ni/Ri is the di viding ratio of one phase locked loop for i=1 . . . n−1.
4. The multiloop phase locked loop (PLL) according to claim 1 , wherein said first voltage controlled oscillator ( 200 , 300 , 400 ) is a coaxial resonator oscillator having a low phase noise.
5. The multiloop phase locked loop (PLL) according to claim 1 , wherein said first programmable divider ( 203 , 303 , 403 ) is a fractional divider based on a sigma-delta conversion.
6. The multiloop phase locked loop (PLL) according to claim 1 , wherein said second programmable divider ( 214 , 314 , 414 , R 1 ), said fourth programmable divider ( 224 , 334 , 494 , R 2 ) and said fifth programmable divider ( 223 , 333 , 443 , N 2 ) are integer dividers and said third programmable divider ( 213 , 313 , 413 , N 1 ) is a fractional divider.
7. A process for configuring the programmable dividers of the multiloop phase locked loop (PLL) circuit as defined in claim 1 , comprising an initialization procedure including the steps of:
determining ( 62 , 91 ) the values of Fout, Fcro_min and Fcro_max corresponding with a locking of said first voltage controlled oscillator ( 200 , 300 , 400 ) so as to produce the desired output frequency (Fout), said determination being performed by continuously varying the ratio of said first programmable dividers ( 203 ) together with a sensing of the voltage present at the output of said first loop filter and determining whether a voltage is higher than one first predetermined threshold;
initiating an iterative loop ( 92 ) for the purpose of testing all possible combinations of values (R 1 , N 1 , R 2 , N 2 , . . . Nn and Rn) used by said programmable dividers;
for each combination, computing ( 94 ) a metrics based on a function stored within a memory depending on the values of Fcro, as well as said dividers values (R 1 , N 1 , R 2 , N 2 , . . . Nn and Rn);
storing ( 95 ) into a memory the value of each metrics together with the current combination of dividers values (R 1 , N 1 , R 2 , N 2 , . . . Nn and Rn); and
testing ( 96 ) whether all combinations have been processed and, if so, retrieving the value of the lowest metrics; and
configuring said programmable dividers with the associated combination of parameters (R 1 , N 1 , R 2 , N 2 , . . . Nn and Rn) being stored into the memory and which correspond to the lowest metrics.
8. An RF frequency synthesizer comprising a multiloop phase locked loop (PLL) circuit as defined in claim 1 .
9. A process for generating a stable and accurate output frequency (Fout), comprising the steps of:
providing a first phase locked loop (PLL) comprising:
a first voltage controlled oscillator ( 200 , 300 , 400 ) generating a first signal having a first frequency (Fcro), said first voltage controlled oscillator having low phase noise and which may be subject to a significant dispersion,
a first phase detector ( 201 , 301 , 401 ) having first and second inputs, said first input receiving a reference frequency (Fref) and said second input receiving the output of a fractional sigma-delta divider ( 203 , 303 , 403 );
said fractional sigma-delta divider ( 203 , 303 , 403 ) receiving said first signal (Fcro); and
a first loop filter ( 202 , 302 , 402 ) having an input connected to the output of said phase detector ( 201 , 301 , 401 ) and having an output connected to the input of said first voltage controlled oscillator VCO ( 200 , 300 , 400 );
providing a second phase locked loop (ELL) comprising:
a second voltage controlled oscillator ( 210 , 310 , 410 ) generating a second signal having a second frequency (F 1 );
a second phase detector ( 211 , 311 , 411 ) having first and second inputs, said first input receiving a signal generated by a first programmable divider ( 214 , 314 , 414 , R 1 ) and said second input receiving the output of a first fractional divider ( 213 , 313 , 413 , N 1 ), wherein said first programmable divider ( 214 , 314 , 414 , R 1 ) and said first fractional divider ( 213 , 313 , 413 , N 1 ) are configured for respectively storing a first variable dividing ration (R 1 ) and a second variable dividing ration (N 1 );
said first programmable divider ( 214 , 314 , 414 , R 1 ) having an input receiving said first;
said first fractional divider ( 213 , 313 , 413 , N 1 ) having an input receiving said second signal; and
a second loop filter ( 212 , 312 , 412 ) having an input receiving the output of said second phase detector and an output connected to an input of said second voltage controlled oscillator ( 210 , 310 , 410 );
providing a third phase locked loop (PLL) comprising:
a third voltage controlled oscillator ( 220 , 330 , 490 ) generating a third signal having a third frequency (F out , F 2 );
a third phase detector ( 221 , 321 , 421 ) having first and second inputs, said first input receiving a signal generated by a second programmable divider ( 224 , 324 , 424 , R 2 ) and said second input receiving the output of a second fractional divider ( 223 , 333 , 443 , N 2 ), wherein said second programmable divider ( 224 , 324 , 424 , R 2 ) and said second fractional divider ( 223 , 333 , 443 , N 2 ) are configured for respectively storing a third variable dividing ratio (R 2 ) and a fourth variable dividing ratio (N 2 );
said second programmable divider ( 224 , 334 , 494 , R 2 ) having an input receiving said first signal;
said second fractional divider ( 223 , 333 , 443 , N 2 ) having an input receiving the output of a first low pass filter ( 225 , 325 , 425 );
said first low pass filter ( 225 , 325 , 425 ) having an input connected to the output of a first mixer ( 219 , 319 , 499 );
said first mixer ( 219 , 319 ) having two inputs respectfully receiving said second and said third signals; and
a third loop filter ( 222 , 322 , 422 ) having an input receiving the output of said third phase detector ( 211 , 331 , 491 ) and an output connected to an input of said third voltage controlled oscillator ( 220 , 330 , 490 );
wherein said third signal has a frequency (Fout) generated in accordance with the relation:
F out=( N 1/ R 1+ N 2/ R 2)* Fcro
wherein said first and second programmable dividers and said first and second fractional dividers are configured with variable dividing ratios selected to optimize
one of the following criteria:
a reduction of the range of one given ratio R 1 /N 1 or R 2 /N 2 ;
a reduction of the range of frequencies used by one among said first, said second and said third phase locked loop (PLL) circuits;
a reduction of spurs impact created by said first, said second and said third voltage controlled oscillators.
10. The process according to claim 9 , further comprising the steps of:
providing a fourth phase locked loop (PLL) comprising:
a fourth voltage controlled oscillator ( 330 ) for generating a fourth signal having a fourth frequency (Fout);
a fourth phase detector ( 331 ) having first and second inputs, said first input receiving a signal generated by a sixth programmable divider ( 334 , R 3 ) and said second input receiving the output of a seventh programmable divider ( 333 , N 3 ), wherein said sixth programmable divider ( 334 , R 3 ) and said seventh programmable divider ( 333 , N 3 ) are configured for restively storing a fifth variable dividing ratio (R 3 ) and a sixth variable dividing ratio (N 3 );
said sixth programmable divider ( 334 , R 3 ) having an input receiving said first signal;
said seventh programmable divider ( 333 , N 3 ) having an input receiving the output of a second low pass filter ( 335 );
said second low pass filter ( 335 ) having an input connected to the output of a second mixer ( 329 );
said second mixer ( 329 ) having two inputs respectively receiving said third signal (F 2 ) and said fourth signal (Fout); and
a fourth loop filter ( 332 ) having an input receiving the output of said fourth phase detector ( 334 ) and an output connected to an input of said fourth voltage controlled oscillator ( 330 );
wherein said fourth signal has a frequency (Fout) which is generated in accordance with the relation:
F out =( N 1/ R 1+ N 2/ R 2+ N 3/ R 3)* F cro
wherein said first, second, third, fourth, fifth and sixth programmable dividers are configured with variable dividing ratios selected to optimize one of the following:
a reduction of the range of one given ratio R 1 /N 1 or R 2 /N 2 or R 3 /N 3 ;
a reduction of the range of frequencies used by one among said first, said second, said third and said fourth multi-loop Phase Locked Loop (PLL) circuit;
a reduction of spurs impact created by said first, said second, said third and said fourth voltage controlled oscillators.
11. The process according to claim 9 , wherein said first voltage controlled oscillator ( 200 , 300 , 400 ) is a coaxial resonator oscillator having a low phase noise.
12. The process according to claim 9 , wherein said fractional sigma-delta divider ( 203 , 303 , 403 ) is a fractional divider based on a sigma-delta conversion.
13. The process according to claim 9 , wherein said first programmable divider ( 214 , 314 , 414 , R 1 ), said second programmable divider ( 224 , 334 , 494 , R 2 ) and said second fractional divider ( 223 , 333 , 443 , N 2 ) are integer dividers and said first fractional divider ( 213 , 313 , 413 , N 1 ) is a fractional divider.