IP Library Granted Patent US 9,799,769
Granted Patent B2
US 9,799,769 · App. 15/399,755 · Granted Oct 24, 2017

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 9,799,769
App. No.
15/399,755
Granted
Oct 24, 2017
Kind
B2
Abstract

A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-shaped structure.

Claims (8)

1. A semiconductor device, comprising:

a substrate having a fin-shaped structure and a second fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure and the second fin-shaped structure;

a gate isolation directly on the second fin-shaped structure;

a gate line on the STI and the first fin-shaped structure, wherein the gate line between the first fin-shaped structure and the gate isolation comprises a L-shaped structure; and

an interlayer dielectric (ILD) layer adjacent to the gate isolation, wherein the gate line comprises a high-k dielectric layer, a work function metal layer on the high-k dielectric layer, and a low resistance metal layer on the work function metal layer, the high-k dielectric layer and the work function metal layer are buried under the low resistance metal layer of the gate line when viewed under top view, and a top surface and a bottom surface of the gate isolation, the ILD layer and the gate line are coplanar, respectively.

2. The semiconductor device of claim 1 , wherein the gate isolation and the ILD layer comprise different material.

3. The semiconductor device of claim 1 , wherein the L-shaped structure comprises a vertical portion and a horizontal portion.

4. The semiconductor device of claim 3 , wherein the vertical portion contacts the fin-shaped structure and the horizontal portion contacts the gate isolation and the STI.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2017
From: LIN, CHIEN-TING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 040867/0620 →