Event-driven design simulation
A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
1. A method comprising:
receiving a specification of a digital circuit, the specification comprising a plurality of instructions that are divided into a plurality of groups of instructions, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group;
maintaining a pending events table in an integrated circuit (IC), each bit of the pending events table indicating absence or presence of a pending event at an input of an instruction in the plurality of instructions;
selecting a group of instructions having pending input events by examining the pending events table;
executing, in the IC, the selected group of instructions to produce outputs to serve as inputs for destination instructions in other groups; and
updating the pending events table by clearing bits in the pending events table that correspond to inputs of the selected group and setting bits in the pending events table that correspond to inputs of the destination instructions.
2. The method of claim 1 , wherein the bits indicating absence or presence of pending events at the inputs of the instructions of the selected group are located in a same word of the pending events table.
3. The method of claim 1 , wherein executing a current instruction in the selected group of instructions further comprises identifying a destination instruction in another group of instructions that receives a fan-out of the current instruction and setting pending input event for the identified destination instruction in the pending events table.
4. The method of claim 1 , wherein the pending events table stores bits that correspond to groups of instructions that are scheduled to execute in a current time step but not instructions that are scheduled to execute in other time steps.
5. The method of claim 1 further comprising advancing a simulation time to a next time step when all bits of the pending events table are cleared.
6. The method of claim 5 further comprising populating the pending events table with contents of a time wheel storage for the next time step.
7. The method of claim 1 further comprising maintaining a time wheel storage for storing pending events at inputs of instructions scheduled to execute in a future time step after a current time step.
8. The method of claim 7 further comprising storing a pending input event into the time wheel storage when a destination instruction is scheduled to execute in a future time step.
9. An integrated circuit (IC) comprising:
an instruction memory storing a plurality of instructions that are sorted into a plurality of groups, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group;
an event manager circuit configured to (i) maintain a pending events table, each bit of the pending events table indicating absence or presence of a pending event at an input of an instruction in the plurality of instructions, (ii) select a group of instructions by identifying an instruction having a pending input event in the pending events table, and (iii) update the pending events table by clearing bits in the pending events table that correspond to inputs of the selected group and setting bits in the pending events table that correspond to inputs of destination instructions; and
a set of processing units configured to execute the selected group of instructions to produce outputs to serve as inputs for the destination instructions.
10. The IC of claim 9 , wherein the bits indicating absence or presence of pending events at the inputs of the instructions of the selected group are located in a same word of the pending events table.
11. The IC of claim 9 , wherein the pending events table stores bits that correspond to groups of instructions that are scheduled to execute in a current time step but not instructions that are scheduled to execute in other time steps.
12. The IC of claim 9 , wherein a simulation time is advanced to a next time step when all bits of the pending events table are cleared, wherein the event manager circuit populates the pending events table with contents of a time wheel storage for the next time step when all bits of the pending events table are cleared.
13. The IC of claim 9 , wherein the event manager circuit is further configured to maintain a time wheel storage for storing pending events at inputs of instructions scheduled to execute in a future time step after a current time step.
14. The IC of claim 13 , wherein the event manager circuit is further configured to storing a pending input event into the time wheel storage when a destination instruction is scheduled to execute in a future time step.
15. A simulation system comprising:
a simulation processor configured to execute a set of compiled models to generate stimulus for testing a design of a digital circuit; and
a simulation accelerator configured to perform acts comprising:
receiving a plurality of instructions emulating the behavior of the digital circuit by applying the generated stimulus, wherein the plurality of instructions are sorted into a plurality of groups of instructions, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group,
maintaining a pending events table in an integrated circuit (IC), each bit of the pending events table indicating absence or presence of a pending event at an input of an instruction in the plurality of instructions;
selecting a group of instructions having pending input events by examining the pending events table;
executing, in the IC, the selected group of instructions to produce outputs to serve as inputs for destination instructions in other groups; and
updating the pending events table by clearing bits in the pending events table that correspond to inputs of the selected group and setting bits in the pending events table that correspond to inputs of the destination instructions.
16. The simulation system of claim 15 , wherein the bits indicating absence or presence of pending events at the inputs of the instructions of the selected group are located in a same word of the pending events table.
17. The simulation system of claim 15 , wherein the pending events table stores bits that correspond to groups of instructions that are scheduled to execute in a current time step but not instructions that are scheduled to execute in other time steps.
18. The simulation system of claim 15 , wherein the simulation accelerator is further configured to advance a simulation time to a next time step when all bits of the pending events table are cleared.
19. The simulation system of claim 18 , wherein the simulation accelerator is further configured to populate the pending events table with contents of a time wheel storage for the next time step.
20. The simulation system of claim 15 , wherein the simulation accelerator is further configured to maintain a time wheel storage for storing pending events at inputs of instructions scheduled to execute in a future time step after a current time step and storing a pending input event into the time wheel storage when a destination instruction is scheduled to execute in a future time step.