Semiconductor substrate
View Patent ↗A semiconductor substrate includes a first exposure shot region, a second exposure shot region aligned with the first exposure shot region in a first direction, first overlay marks, second overlay marks, and a scribe lane. The first overlay marks are disposed in a first peripheral part of the first exposure shot region. The second overlay marks are disposed in a second peripheral part of the second exposure shot region. The scribe lane is disposed between a first center part of the first exposure shot region and a second center part of the second exposure shot region. A center point of the first overlay mark disposed within the scribe lane and a center point of the second overlay mark which is closest to the first overlay mark are arranged in a second direction different from the first direction for increasing the distance between the first and the second overlay marks.
1. A semiconductor substrate, comprising:
a first exposure shot region comprising:
a first center part; and
a first peripheral part encompassing the first center part;
a second exposure shot region adjoining the first exposure shot region, wherein the first exposure shot region and the second exposure shot region are aligned in a first direction, and the second exposure shot region comprises:
a second center part; and
a second peripheral part encompassing the second center part;
a plurality of first overlay marks disposed in the first peripheral part;
a plurality of second overlay marks disposed in the second peripheral part;
a scribe lane disposed between the first center part and the second center part in the first direction, wherein at least one of the first overlay marks and at least one of the second overlay marks are disposed within the scribe lane, and a center point of the first overlay mark within the scribe lane and a center point of the second overlay mark which is closest to the first overlay mark are arranged in a second direction different from the first direction;
a first logo region disposed in the first peripheral part and within the scribe line, wherein the first logo region is disposed adjacent to the first overlay mark within the scribe lane in a third direction orthogonal to the first direction; and
a second logo region disposed in the second peripheral part and within the scribe line, wherein the second logo region is disposed adjacent to the second overlay mark within the scribe lane in the third direction, there is not any overlay mark disposed in the first logo region and the second logo region, and there is not any alignment mark disposed in the first logo region and the second logo region.
2. The semiconductor substrate according to claim 1 , wherein there is not any overlay mark disposed between the second center part and the first overlay mark within the scribe lane in the first direction.
3. The semiconductor substrate according to claim 1 , wherein there is not any overlay mark disposed between the first center part and the second overlay mark within the scribe lane in the first direction.
4. The semiconductor substrate according to claim 1 , wherein the second direction is not parallel and not orthogonal to the first direction.
5. The semiconductor substrate according to claim 1 , wherein a distance between the center point of the first overlay mark within the scribe lane and the center point of the second overlay mark which is closest to the first overlay mark is larger than a distance between the center point of the first overlay mark and a center point of the second logo region.
6. The semiconductor substrate according to claim 1 , wherein a distance between the center point of the first overlay mark within the scribe lane and the center point of the second overlay mark which is closest to the first overlay mark is larger than a distance between the center point of the second overlay mark and a center point of the first logo region.
7. The semiconductor substrate according to claim 1 , wherein the first logo region is disposed between the first center part and the second overlay mark within the scribe lane in the first direction.
8. The semiconductor substrate according to claim 1 , wherein the second logo region is disposed between the second center part and the first overlay mark within the scribe lane in the first direction.
9. The semiconductor substrate according to claim 1 , wherein a center point of the first logo region and a center point of the second logo region are arranged in a direction different from the first direction.
10. The semiconductor substrate according to claim 1 , further comprises vernier patterns disposed in the first logo region and/or the second logo region.
11. The semiconductor substrate according to claim 1 , wherein the first center part and/or the second center part comprises:
a plurality of die regions; and
a plurality of sub scribe lanes, wherein the die regions are separated from one another by the sub scribe lanes.
12. The semiconductor substrate according to claim 1 , wherein a distance between the center point of the first overlay mark within the scribe lane and the center point of the second overlay mark which is closest to the first overlay mark is larger than a width of the first overlay mark and/or a width of the second overlay mark in the first direction.
13. The semiconductor substrate according to claim 1 , wherein two of the first overlay marks and two of the second overlay marks are disposed within the scribe lane between the first center part and the second center part in the first direction.