3D vertical FET with top and bottom gate contacts

1. A semiconductor device, comprising:

a vertical transistor having a gate structure disposed about a channel region thereof, the vertical transistor having a top side above the gate structure and a bottom side below the gate structure;

top metallization structures in the top side above the gate structure having at least one connection to the vertical transistor on the top side;

bottom metallization structures in the bottom side below the gate structure having at least one connection to the vertical transistor on the bottom side and the bottom side including a power rail and a ground rail buried in a common dielectric layer in a common plane parallel to a plane of the gate structure and connected to at least one of the bottom metallization structures of the bottom side.

2. The device as recited in claim 1 , wherein the gate structure is contacted on the top side and the bottom side by gate contacts.

3. The device as recited in claim 1 , wherein the gate contacts are formed on opposite sides of a same gate structure on the top side and the bottom side.

4. The device as recited in claim 1 , wherein the vertical transistor is contacted on the top side and the bottom side.

5. The device as recited in claim 1 , wherein the top side includes far end of the line structures and the bottom side includes back end of the line (BEOL) structures.

6. The device as recited in claim 1 , wherein the bottom metallization structures on the bottom side connect to conductive bumps on a back side of the device.

7. The device as recited in claim 1 , wherein the vertical transistor is a part of a logic device and the logic device connects to the top metallization structures on the top side and the bottom metallization structures on the bottom side.

8. The device as recited in claim 7 , wherein the logic device includes a logic device from a five track cell library.

9. A semiconductor device, comprising:

vertical transistors sharing a same gate structure, the vertical transistors having a channel region and source and drain regions disposed above and below the channel region, the vertical transistors forming a plane to provide a top side region above the plane and a bottom side below the plane;

top side metallization structures formed above the plane and including one or more connections to the vertical transistors and the gate structure;

bottom side metallization structures formed below the plane and including one or more connections to the vertical transistors and the gate structure;

a power rail buried in a dielectric layer below the plane and connected to at least one of the bottom side metallization structures; and

a ground rail buried in the dielectric below the plane in a common plane with the power rail and connected to at least one of the bottom side metallization structures.

10. The device as recited in claim 9 , wherein the gate structure is contacted by a top side contact above the plane and a bottom side contact below the plane.

11. The device as recited in claim 9 , wherein the top side contact and the bottom side contact are formed on opposing sides of the gate structure.

12. The device as recited in claim 9 , wherein the top side metallization structures include far end of the line structures and the bottom side metallization structures include back end of the line (BEOL) structures.

13. The device as recited in claim 9 , wherein the bottom side metallization structures connect to conductive bumps on a back side of the device.

14. The device as recited in claim 9 , wherein the vertical transistors are a part of a logic device and the logic device connects to the top side metallization structures and the bottom side metallization structures.

15. The device as recited in claim 14 , wherein the logic device includes a logic device from a five track cell library.