Semiconductor device and method of manufacturing the same

1. A semiconductor device comprising:

a semiconductor chip;

a power transistor and a capacitor element electrically coupled with the power transistor formed on the semiconductor chip,

wherein the power transistor includes:

a source electrode and a drain electrode spaced from each other in a thickness direction of the semiconductor chip; and

a gate electrode which controls turning on/off a current flowing between the drain electrode and the source electrode,

wherein the capacitor element includes:

the source electrode being a first electrode;

a second electrode facing to the first electrode; and

a capacitor insulating film formed between the first electrode and the second electrode,

wherein the second electrode is electrically coupled with the drain electrode,

wherein a gate pad electrically coupled with the gate electrode, the source electrode, and the second electrode is formed over a main surface of the semiconductor chip, and

wherein, in a plan view, over the main surface of the semiconductor chip, a second electrode exposure region, where the second electrode is exposed, and a source electrode exposure region, where the source electrode is exposed, are formed, and the gate pad is exposed.

2. The semiconductor device according to claim 1 , wherein the second electrode is contained in the source electrode in the plan view.

3. The semiconductor device according to claim 1 , wherein the power transistor and the capacitor element are arranged in a laminated manner in the thickness direction of the semiconductor chip.

4. The semiconductor device according to claim 1 , wherein the power transistor comprises:

a semiconductor substrate;

the drain electrode formed over a back surface of the semiconductor substrate;

a drift layer formed over a main surface of the semiconductor substrate;

a channel layer formed over the drift layer;

a trench passing through the channel layer and reaching the drift layer;

a gate insulating film formed over an inner wall of the trench;

a gate electrode embedded in the trench through the gate insulating film;

a source region in contact with the trench and formed over a surface of the channel layer; and

the source electrode electrically coupled with the source region.

5. The semiconductor device according to claim 4 ,

wherein the source electrode is formed ranging from over the source region to over the gate electrode, and

wherein an insulating film is interposed between the source electrode and the gate electrode.

6. The semiconductor device according to claim 1 comprising:

a chip mounting part; and

the semiconductor chip mounted over the chip mounting part, and

wherein the drain electrode is formed over a back surface of the semiconductor chip.

7. The semiconductor device according to claim 6 , comprising:

a drain lead joined to the chip mounting part;

a source lead spaced from the chip mounting part; and

a gate lead spaced from the chip mounting part.

8. The semiconductor device according to claim 7 ,

wherein the source electrode exposure region and the source lead are coupled by a first conductive member,

wherein the gate pad and the gate lead are coupled by a second conductive member, and

wherein the upper electrode exposure region and the chip mounting part are coupled by a third conductive member.

9. The semiconductor device according to claim 8 ,

wherein the source electrode exposure region and the source lead are coupled by a plurality of first conductive members, and

wherein the upper electrode exposure region and the chip mounting part are coupled by a plurality of third conductive members.

10. The semiconductor device according to claim 7 ,

wherein the source electrode exposure region and the source lead are coupled by a first conductive member,

wherein the gate pad and the gate lead are coupled by a second conductive member,

wherein a drain pad electrically coupled with the upper electrode is exposed over the surface of the semiconductor chip, and

wherein the drain pad and the chip mounting part are coupled by a third conductive member.

11. The semiconductor device according to claim 10 , wherein the plural drain pads electrically coupled with the upper electrode over the surface of the semiconductor chip are present.

12. The semiconductor device according to claim 1 , wherein a film thickness of the capacitor insulating film is 50 nm or more and 250 nm or less.

13. A semiconductor device comprising:

a semiconductor chip; and

a power transistor and a capacitor element electrically coupled with the power transistor formed on the semiconductor chip,

wherein the power transistor includes:

an emitter electrode and a collector electrode spaced from each other in a thickness direction of the semiconductor chip; and

a gate electrode which controls turning on/off a current flowing between the collector electrode and the emitter electrode,

wherein the capacitor element includes:

the emitter electrode being a first electrode;

a second electrode facing to the first electrode; and

a capacitor insulating film formed between the first electrode and the second electrode,

wherein the second electrode is electrically coupled with the emitter electrode,

wherein a gate pad electrically coupled with the gate electrode, the emitter electrode, and the second electrode is formed over a main surface of the semiconductor chip, and

wherein, in a plan view, over the main surface of the semiconductor chip, a second electrode exposure region, where the second electrode is exposed, and an emitter electrode exposure region, where the emitter electrode is exposed, are formed, and the gate pad is exposed.

14. The semiconductor device according to claim 13 , wherein the power transistor is an insulated gate bipolar transistor.

15. A method of manufacturing a semiconductor device comprising a power transistor and a capacitor element electrically coupled with the power transistor,

wherein the power transistor includes:

a source electrode and a drain electrode spaced from each other; and

a gate electrode which controls turning on/off a current flowing between the drain electrode and the source electrode,

wherein the capacitor element includes:

the source electrode being a first electrode;

a second electrode facing to the first electrode; and

a capacitor insulating film formed between the first electrode and the second electrode,

wherein the second electrode is electrically coupled with the drain electrode,

wherein a gate pad electrically coupled with the gate electrode, the source electrode, and the second electrode is formed over a main surface of the semiconductor chip, and

wherein, in a plan view, over the main surface of the semiconductor chip, a second electrode exposure region, where the second electrode is exposed, and a source electrode exposure region, where the source electrode is exposed, are formed, and the gate pad is exposed,

the method comprising the steps of:

(a) providing a semiconductor substrate having a drift layer formed over a surface thereof and a channel layer formed over the drift layer;

(b) forming a trench passing through the channel layer and reaching the drift layer;

(c) forming a gate insulating film over an inner wall of the trench;

(d) forming a gate electrode to be embedded in the trench through the gate insulating film;

(e) after the step (d), forming a source region over a surface of the channel layer so as to be in contact with the trench;

(f) after the step (e), forming an insulating film covering an upper surface of the gate electrode;

(g) after the step (f), forming the source electrode to be coupled with the source region;

(h) forming the capacitor insulating film over the source electrode;

(i) forming the second electrode over the capacitor insulating film; and

(j) forming the drain electrode over a back surface of the semiconductor substrate.