Non-volatile memory device and program method of a non-volatile memory device
A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.
1. A method of programming a non-volatile memory, the method comprising:
executing at least two program loops on memory cells in a selected word line;
generating a fail bit trend based on a result of executing each of the at least two program loops;
predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells for having a target threshold voltage distribution, based on the generated fail bit trend; and
changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.
2. The method of claim 1 , wherein the generating of the fail bit trend comprises generating the fail bit trend by using a number of fail bits generated by executing each of the at least two program loops.
3. The method of claim 2 , wherein the fail bit trend corresponds to an amount of a change in the number of fail bits generated by executing each of the at least two program loops.
4. The method of claim 1 , wherein the predicting of the plurality of program loops comprises:
predicting a number of N fail bits that is lower than a number of reference fail bits, based on the fail bit trend; and
predicting a program loop corresponding to the predicted number of N fail bits as the N program loop.
5. The method of claim 1 , wherein the changing of the level of the N program voltage comprises generating a number of M fail bits when an M program loop that is a change reference program loop is executed on the memory cells, and
the level of the N program voltage is changed based on the number of M fail bits.
6. The method of claim 5 , wherein the M program loop comprises a program loop that is selected from among the plurality of program loops that are predicted.
7. The method of claim 5 , wherein the M program loop comprises an N−1 program loop that is executed immediately sequentially prior to when the N program loop is executed.
8. The method of claim 5 , wherein the changing of the level of the N program voltage further comprises generating an M reference range corresponding to the M program loop based on the number of reference fail bits and the fail bit trend, and
the level of the N program voltage is changed based on whether the number of M fail bits is comprised in the M reference range.
9. The method of claim 8 , wherein, when the number of M fail bits is comprised in the M reference range, the level of the N program voltage decreases in proportion to a decrease in the number of M fail bits.
10. The method of claim 8 , wherein the changing of the level of the N program voltage comprises changing the level of the N program voltage by referring to a voltage level change table, which is set based on the M reference range, and using voltage level change values corresponding to the number of M fail bits.
11. The method of claim 1 , further comprising:
determining a fail bit trend generation timing based on at least one of an execution state in which the plurality of program loops are executed on the memory cells and a number of the plurality of program loops executed on the memory cells.
12. A non-volatile memory device, comprising:
a memory cell array comprising a plurality of memory cells that are targeted for program loop execution; and
a controller configured to execute a plurality of program loops on the plurality of memory cells,
wherein the controller comprises:
a fail bit trend generator configured to generate a fail bit trend based on results of executing at least two of the plurality of program loops that are executed on the plurality of memory cells;
a program loop prediction unit configured to predict the plurality of program loops to be executed on the plurality of memory cells based on the fail bit trend; and
a program voltage level controller configured to change a level of a program voltage provided when a last program loop is executed on the plurality of memory cells for having a target threshold voltage distribution, based on a result of predicting the plurality of program loops.
13. The non-volatile memory device of claim 12 , wherein the fail bit trend generator is further configured to generate the fail bit trend corresponding to an amount of a change in a number of fail bits that are generated by executing each of the plurality of program loops.
14. The non-volatile memory device of claim 13 , wherein the program loop prediction unit is further configured to predict, as the last program loop, a program loop corresponding to the number of fail bits that is predicted to be lower than a number of reference fail bits, based on the fail bit trend.
15. The non-volatile memory device of claim 12 , wherein the program voltage level controller is further configured to select a change reference program loop from among the plurality of program loops that are predicted and change the level of the program voltage based on a number of fail bits that are generated by executing the change reference program loop on the plurality of memory cells.
16. A method of programming a non-volatile memory, the method comprising:
executing at least two program loops on memory cells in a selected word line and identifying memory cells with voltage levels below a threshold;
generating, based on a result of executing each of the at least two program loops, a fail bit trend identifying a trend in a number of memory cells identified with voltage levels below the threshold;
projecting a number of program loops comprising an N program loop to be executed last on the memory cells for having a target threshold voltage distribution, based on the generated fail bit trend; and
changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.
17. The method of claim 16 , wherein the fail bit trend is generated using a number of fail bits in memory cells identified with voltage levels below the threshold.
18. The method of claim 17 , wherein the fail bit trend corresponds to an amount of a change in the number of fail bits generated by executing each of the at least two program loops.
19. The method of claim 16 , further comprising:
determining a fail bit trend generation timing based on at least one of an execution state in which the plurality of program loops are executed on the memory cells and a number of the plurality of program loops executed on the memory cells.
20. The method of claim 16 ,
wherein the memory cells are in a memory cell array and are targeted for program loop execution, and
wherein the plurality of program loops on the plurality of memory cells are executed by a controller that is configured to generate the fail bit trend.