Molded image sensor chip scale packages and related methods

1. A chip scale package comprising:

an image sensor comprising a first side and a second side;

a first cavity wall and a second cavity wall coupled to the first side of the image sensor and extending therefrom, wherein the first cavity wall and the second cavity wall form a cavity over the image sensor;

a transparent layer coupled to the first cavity wall and to the second cavity wall;

a redistribution layer (RDL) coupled to the second side of the image sensor;

at least one interconnect directly coupled to the RDL; and

a mold material, wherein the mold material encapsulates a portion of the RDL, a portion of the image sensor, a side of each cavity wall, and a portion of the transparent layer; and

wherein the mold material directly covers a first interface between the transparent layer and the first cavity wall and a second interface between the transparent layer and the second cavity wall.

2. The package of claim 1 , wherein the mold material extends along a portion of the RDL, a side of each cavity wall, and a portion of the transparent layer.

3. The package of claim 1 , wherein the mold material forms a layer parallel with the image sensor and extends along a portion of the RDL, a side of each cavity wall, and a portion of the transparent layer in a direction perpendicular to the image sensor.

4. The package of claim 1 , wherein the mold material extends into a groove formed in the transparent layer.

5. The package of claim 1 , wherein the interconnect is one of a solder ball, a pillar, a copper ball, a gold ball, and any combination thereof.

6. The package of claim 1 , wherein the mold material is a laminatable molding material.

7. A method of forming a chip scale package comprising:

providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;

coupling the first side of the wafer to a first side of a plurality of cavity walls;

coupling a transparent layer to a second side of the plurality of cavity walls;

coupling a redistribution layer (RDL) to the second side of the wafer;

forming an interconnect array on the RDL;

forming a plurality of notches between each image sensor, wherein the plurality of notches extends from the image sensor into the transparent layer;

placing a mold material over the interconnect array to encapsulate a portion of the RDL;

filling the plurality of notches with the mold material, wherein the mold material directly covers a plurality of interfaces between the transparent layer and the plurality of cavity walls; and

singulating each image sensor at each notch of the plurality of notches to form a plurality of chip scale packages.

8. The method of claim 7 , wherein singulating further comprises forming a layer of the mold material that extends into a groove of the transparent layer.

9. The method of claim 7 , wherein filling the plurality of notches with the mold material further comprises extending the mold material along a portion of the RDL, a side of each cavity wall of the plurality of cavity walls, and a portion of the transparent layer.

10. The method of claim 7 , wherein the mold material is one of a solid mold material and a liquid mold material.

11. The method of claim 7 , wherein the mold material is laminatable.

12. The method of claim 11 , wherein placing the mold material over the interconnect array further comprises laminating the mold material under vacuum conditions.

13. The method of claim 7 , wherein the notch formed ends in the transparent layer.

14. The method of claim 7 , wherein the interconnect array comprises one of a ball grid array, a land grid array, a pin grid array, a pillar grid array, and any combination thereof.

15. A method of forming a chip scale package comprising:

providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;

coupling the first side of a wafer to a first side of a plurality of cavity walls;

coupling a transparent layer to a second side of the plurality of cavity walls;

coupling a redistribution layer (RDL) to the second side of the wafer;

forming an interconnect array on the RDL;

forming a plurality of notches between each image sensor, wherein the plurality of notches extends from the image sensor into the transparent layer;

placing a mold material over the interconnect array;

laminating the mold material to press the interconnect array through the mold material to encapsulate a portion of the RDL;

laminating the mold material into each notch of the plurality of notches, wherein the mold material directly covers a plurality of interfaces between the transparent layer and the plurality of cavity walls; and

singulating each image sensor at each notch of the plurality of notches to form a plurality of chip scale packages.

16. The method of claim 15 , wherein singulating further comprises forming a layer of the mold material that extends into a groove of the transparent layer.

17. The method of claim 15 , wherein filing the plurality of notches with the mold material further comprises extending the mold material along a portion of the RDL, a side of each cavity wall of the plurality of cavity walls, and a portion of the transparent layer.

18. The method of claim 15 , wherein the mold material is laminated at a temperature between 30-100 degrees Celsius and a pressure between 0-50 MPa.

19. The method of claim 15 , wherein the interconnect array comprises one of a ball grid array, a land grid array, a pin grid array, a pillar grid array, and any combination thereof.