Power-reduced redundant array of independent memory (RAIM) system
View Patent ↗Embodiments include techniques used for a power-reduced redundant array of independent memory RAIM system. The technique includes blocking commands to one or more memory modules of the RAIM system and reading data from one or more unblocked memory modules. The technique also includes applying a power channel mark for one or more blocked memory modules, the power channel mark indicating the one or more blocked memory modules to a decoder for error correction.
1. A computer-implemented method for power-reduced operation of a redundant array of independent memory (RAIM) system, the method comprising:
marking one or more memory modules of the RAIM system with a power channel mark based on determining an error associated with received commands;
blocking the commands to one or more memory modules based on the error;
reading data from one or more unblocked memory modules of the one or more memory modules, responsive to blocking the commands to one or more memory modules; and
providing the power channel mark to a decoder for error correction, wherein no power is supplied to the one or more blocked memory modules based on the power channel mark.
2. The computer-implemented method of claim 1 , wherein the blocked command is a fetch command and the fetch command is provided to a memory controller to retrieve data from one or more memory modules.
3. The computer-implemented method of claim 1 , further comprising disabling the blocking when non-power channel marks are present, wherein the non-power channel marks comprise global channel marks, per-rank channel marks, and/or hierarchical channel marks.
4. The computer-implemented method of claim 1 , further comprising responsive to determining errors in data retrieved from the one or more memory modules are present, disabling the power channel mark and re-performing a fetch to recover data in based on the errors.
5. The computer-implemented method of claim 4 , wherein the errors comprise CRC errors.
6. The computer-implemented method of claim 1 , comprising using a hierarchical priority scheme for managing channel marks to prevent multiple simultaneous channel marks resulting in uncorrectable errors.
7. The computer-implemented method of claim 1 , further comprising updating an error correction code supplied to the decoder based on the power channel mark.
8. A power-reduced redundant array of independent memory (RAIM) system, the system comprising
a processor;
a non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium being coupled to the processor;
the processor configured to:
mark one or more memory modules of the RAIM system with a power channel mark based on determining an error associated with received commands;
block the commands to the one or more memory modules based on the error;
read data from one or more unblocked memory modules of the one or more memory modules, responsive to blocking the commands to one or more memory modules; and
provide the power channel mark to a decoder for error correction, wherein no power is supplied to the one or more blocked memory modules based on the power channel mark.
9. The system of claim 8 , wherein the blocked command is a fetch command and the fetch command is provided to a memory controller to retrieve data from one or more memory modules.
10. The system of claim 8 , the processor being further configured to disable the blocking when non-power channel marks are present, wherein the non-power channel marks comprise global channel marks, per-rank channel marks, and/or hierarchical channel marks.
11. The system of claim 8 , further comprising responsive to determining errors in data retrieved from the one or more memory modules are present, the processor being further configured to disable the power channel mark and re-perform a fetch to recover data in the presence of the errors.
12. The system of claim 11 , wherein the errors comprise CRC errors.
13. The system of claim 8 , the processor being further configured to use a hierarchical priority scheme for managing channel marks to prevent multiple simultaneous channel marks resulting in uncorrectable errors.
14. The system of claim 8 , the processor further configured to update an error correction code based on the power channel mark.
15. A computer program product for operating a power-reduced redundant array of independent memory (RAIM) system, the computer program product comprising:
a non-transitory computer readable storage medium having stored thereon first program instructions executable by a processor to cause the processor to:
mark one or more memory modules of the RAIM system with a power channel mark based on determining an error associated with received commands;
block the commands to one or more memory modules based on the error;
read data from one or more unblocked memory modules of the one or more memory modules, responsive to blocking the commands to one or more memory modules; and
provide the power channel mark to a decoder for error correction, wherein no power is supplied to the one or more blocked memory modules based on the power channel mark.
16. The computer program product of claim 15 , wherein the instructions are further executable by a processor to cause the processor to disable the blocking when non-power channel marks are present, wherein the non-power channel marks comprise global channel marks, per-rank channel marks, and/or hierarchical channel marks.
17. The computer program product of claim 15 , wherein the instructions are further executable by a processor to cause the processor to responsive to determining errors in data retrieved from the one or more memory modules are present, disable the power channel mark and re-perform a fetch to recover data in the presence of the errors.
18. The computer program product of claim 15 , wherein the instructions are further executable by a processor to cause the processor to update an error correction code based on the power channel mark.