Semiconductor device capable of high-voltage operation
A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
1. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type;
a second well region formed in a portion of the first well region, having the first conductivity type;
a first gate structure formed over a portion of the second well region and a portion of the first well region, wherein a first dielectric layer of the first gate structure has a constant thickness;
a first doped region formed in a portion of the second well region, having the second conductivity type; and
a second doped region formed in a portion of the first well region, having the second conductivity type;
and
a second gate structure formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
2. The semiconductor device as claimed in claim 1 , wherein the first gate structure comprises a first conductive layer formed over the first dielectric layer, and the second gate structure comprises a second dielectric layer and a second conductive layer formed over the second dielectric layer.
3. The semiconductor device as claimed in claim 2 , further comprising:
an isolation element disposed in a portion of the semiconductor substrate;
a third conductive layer formed over the isolation element;
a third dielectric layer formed over the third conductive layer; and
a fourth conductive layer formed over the third dielectric layer.
4. The semiconductor device as claimed in claim 3 , wherein the third conductive layer, the third dielectric layer, and the fourth conductive layer form a capacitor.
5. The semiconductor device as claimed in claim 3 , wherein the third conductive layer and the second conductive layer are formed simultaneously.
6. The semiconductor device as claimed in claim 3 , wherein the third dielectric layer and the second dielectric layer are formed simultaneously.
7. The semiconductor device as claimed in claim 3 , wherein the fourth conductive layer and the second conductive layer are formed simultaneously.
8. The semiconductor device as claimed in claim 3 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
9. The semiconductor device as claimed in claim 3 , wherein the first dielectric layer has a thickness of about 23-140 Å, and the second and third dielectric layers have a thickness of about 200-1200 Å.
10. The semiconductor device as claimed in claim 3 , wherein the second gate structure covers about 20%-80% of a top surface of the first gate structure.
11. The semiconductor device as claimed in claim 3 , wherein second conductive layer comprises polysilicon or metal.
12. A method for forming a semiconductor device, comprising:
providing a semiconductor structure comprising:
a semiconductor substrate having a first conductivity type;
a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type;
a second well region formed in a portion of the first well region, having the first conductivity type;
a first doped region formed in a portion of the second well region, having the second conductivity type;
a second doped region formed in a portion of the first well region, having the second conductivity type; and
a first gate structure formed over a portion of the second well region and a portion of the first well region, wherein a first dielectric layer of the first gate structure has a constant thickness;
and
forming a second gate structure over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
13. The method as claimed in claim 12 , wherein the first gate structure comprises a first conductive layer formed over the first dielectric layer, and the second gate structure comprises a second dielectric layer and a second conductive layer formed over the second dielectric layer.
14. The method as claimed in claim 13 , wherein the first dielectric layer has a thickness of about 23-140 Å, and the second dielectric layer has a thickness of about 200-1200 Å.
15. The method as claimed in claim 12 , wherein the second gate structure covers about 20%-80% of a top surface the first gate structure.
16. The method as claimed in claim 13 , wherein the second conductive layer comprises polysilicon or metal.