Six-transistor static random access memory cell and operation method thereof

1. A six transistor static random-access memory (6T SRAM) cell comprising:

a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node;

a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor;

a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, wherein the switch transistor is configured to be deactivated in a writing mode; and

an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor, wherein the 6T SRAM cell comprises only 6 transistors, and a gate of the switch transistor is not coupled to a gate of the access transistor.

2. The 6T SRAM cell of claim 1 , wherein the switch transistor comprises an NMOS transistor.

3. The 6T SRAM cell of claim 1 , wherein the switch transistor is configured to be activated in a standby mode and a reading mode.

4. The 6T SRAM cell of claim 1 , wherein the gate of the switch transistor is coupled to a mode line.

5. The 6T SRAM cell of claim 1 , wherein the gate of the access transistor is coupled to a word line.

6. The 6T SRAM cell of claim 1 , wherein the access transistor is configured to couple a bit line.

7. The 6T SRAM cell of claim 1 , wherein the gates of the first pull-up transistor and the first pull-down transistor are coupled to each other.

8. The 6T SRAM cell of claim 1 , further comprising two read transistors electrically connected to the 6T SRAM cell.

9. A method of operating a six transistor static random access memory (6T SRAM) cell, the method comprising:

providing a six transistor static random-access memory (6T SRAM) cell comprising:

a first inverter comprising a first pull-up transistor and a first pull-down transistor and a first storage node;

a second inverter comprising a second pull-up transistor, a second pull-down transistor and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor;

a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, wherein the switch transistor is configured to be deactivated in a writing mode; and

an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor, wherein the 6T SRAM cell comprises only 6 transistors, and a gate of the switch transistor is not coupled to a gate of the access transistor;

deactivating the switch transistor during a write operation;

writing a data value in the second storage node through the access transistor; and

activating the switch transistor after the data value is written in the second storage.

10. The method of claim 9 , wherein the switch transistor comprises an NMOS transistor.

11. The method of claim 9 , wherein the gate of the switch transistor is coupled to a mode line.

12. The method of claim 11 , wherein the gate of the access transistor is coupled to a word line.

13. The method of claim 11 , wherein the mode line is deactivated before the word line is activated during the write operation.

14. The method of claim 13 , further comprising performing a standby operation after the writing operation is performed, and wherein the mode line is activated before the word line is deactivated during the standby operation.

15. The method of claim 9 , further comprising providing two read transistors electrically connected to the 6T SRAM cell.