IP Library Granted Patent US 9,773,797
Granted Patent B2
US 9,773,797 · App. 15/414,110 · Granted Sep 26, 2017

Non-volatile memory device

Inventor: Hiroki Yamashita (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11556H01L27/11519H01L27/11524H01L29/42328H01L29/512H01L29/788
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Quick Facts
Patent No.
US 9,773,797
App. No.
15/414,110
Granted
Sep 26, 2017
Kind
B2
Abstract

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Claims (52)

1. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells stacked in a first direction and electrically connected in series; and

a selection transistor provided above the memory cells,

at least one of the memory cells including:

a control gate electrode;

a first channel extending in the first direction through the control gate electrode;

a first insulating core film provided inside the first channel;

a conductive layer provided between the control gate electrode and the first channel;

a first insulating film provided between the conductive layer and the first channel; and

a second insulating film provided between the control gate electrode and the conductive layer,

a width of the conductive layer in the first direction being narrower than a width of the second insulating film in the first direction, and the control gate electrode surrounding an outer periphery of the conductive layer via the second insulating film in a plane perpendicular to the first direction, and

the selection transistor including:

a selection gate electrode; and

a second channel extending in the first direction through the selection gate electrode, the second channel being connected to one end of the first channel and not overlapping with the control gate electrode when projected from the first direction.

2. The device according to claim 1 , wherein the conductive layer includes at least one of a conductive film containing silicon, a metal film, and a conductive film containing a metal oxide.

3. The device according to claim 1 , wherein the conductive layer has a stacked structure including a third insulating film and at least one of a conductive film containing silicon, a metal film, and a conductive film containing a metal oxide.

4. The device according to claim 1 , wherein

the control gate electrode and an interlayer insulating film are alternately arranged in the first direction,

the first channel is provided inside a first hole piercing the control gate electrode and the interlayer insulating film alternately arranged, and

the first insulating film extends in the first direction along the first channel.

5. The device according to claim 4 , wherein

the second channel is provided inside a second hole piercing the selection gate electrode, and

a dimension of the second hole is different from that of the first hole in a direction perpendicular to the first direction.

6. The device according to claim 1 , wherein the second insulating film includes an oxide containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

7. The device according to claim 1 , wherein the second insulating film includes an oxynitride containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

8. The device according to claim 1 , wherein the second insulating film has a stacked structure including an oxide containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum and an oxynitride containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

9. The device according to claim 1 , wherein the selection gate electrode is provided to oppose the second channel in a direction perpendicular to the first direction and a gate insulating film is provided between the selection gate electrode and the second channel, the conductive layer being not provided between the selection gate electrode and the second channel.

10. The device according to claim 1 , wherein a width of the selection gate electrode in the first direction is larger than a width of the control gate electrode in the first direction.

11. The device according to claim 1 , wherein a position of the second channel is shifted from that of the first channel in a direction perpendicular to the first direction.

12. The device according to claim 1 , wherein the selection transistor further includes a second insulating core film provided inside the second channel.

13. The device according to claim 1 , wherein the conductive layer has a ring shape.

14. The device according to claim 13 , wherein the conductive layer has two side surfaces opposing to each other, and one of the side surfaces has a length longer than that of the other of the side surfaces in the first direction.

15. The device according to claim 1 , wherein the conductive film, the first insulating film and the first channel are provided concentrically when projected from the first direction.

16. A nonvolatile semiconductor memory device comprising:

a plurality of floating gate type memory cells stacked in a first direction and electrically connected in series; and

a selection transistor provided above the memory cells,

at least one of the memory cells including:

a control gate electrode;

a first channel extending in the first direction through the control gate electrode;

a first insulating core film provided inside the first channel;

a polysilicon film provided between the control gate electrode and the first channel;

a first insulating film provided between the polysilicon film and the first channel; and

a second insulating film provided between the control gate electrode and the polysilicon film,

a width of the polysilicon film in the first direction being narrower than a width of the second insulating film in the first direction, and

the control gate electrode surrounding an outer periphery of the polysilicon film via the second insulating film in a plane perpendicular to the first direction, and

the selection transistor including:

a selection gate electrode; and

a second channel extending in the first direction through the selection gate electrode, the second channel being connected to one end of the first channel and not overlapping with the control gate electrode when projected from the first direction.

17. The device according to claim 16 , wherein the selection gate electrode is provided to oppose the second channel in a direction perpendicular to the first direction and a gate insulating film is provided between the selection gate electrode and the second channel, and no conductive layer is provided between the selection gate electrode and the second channel.

18. The device according to claim 16 , wherein a width of the selection gate electrode in the first direction is larger than a width of the control gate electrode in the first direction.

19. The device according to claim 16 , wherein a position of the second channel is shifted from that of the first channel in a direction perpendicular to the first direction.

20. The device according to claim 16 , wherein the selection transistor further includes a second insulating core film provided inside the second channel.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
Continuity (3)
Continuation 14483259 · Sep 11, 2014
Provisional Application 62023031 · Jul 10, 2014
Related Publication 20170133393A1 · May 11, 2017