IP Library Granted Patent US 10,782,316
Granted Patent B2
US 10,782,316 · App. 15/416,510 · Granted Sep 22, 2020

Socket side thermal system

Inventor: Jerry Ihor Tustaniwskyj (Mission Viejo, CA)
Assignee: DELTA DESIGN, INC.
G01R1/0458G01R31/2874
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Quick Facts
Patent No.
US 10,782,316
App. No.
15/416,510
Granted
Sep 22, 2020
Kind
B2
Abstract

An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.

Claims (19)

1. An integrated circuit device testing system comprising:

a socket configured to receive an integrated circuit device, wherein the socket comprises:

a base member having a plurality of electrical contacts;

a circuit board supported by the base member via at least one spring, the circuit board having a plurality of openings configured to receive electrical contacts of the integrated circuit device and electrically engage with the electrical contacts of the base member through the openings of the circuit board; and

at least one conductive trace positioned on or within the circuit board and extending around the plurality of openings of the circuit board to detect temperature of the integrated circuit device when the integrated circuit device is engaged with the electrical contacts of the base member, the conductive trace being made of a material with a resistivity that is a function of temperature; and

a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace while the integrated circuit device is engaged with the electrical contacts of the base member.

2. The integrated circuit device testing system of claim 1 , wherein the circuit board comprises a flexible circuit board.

3. The integrated circuit device testing system of claim 1 , wherein the at least one conductive trace is etched in the circuit board.

4. The integrated circuit device testing system of claim 1 , wherein the conductive trace comprises copper.

5. The integrated circuit device testing system of claim 1 , wherein the openings are arranged in columns corresponding to columns of electrical contacts of the integrated circuit device, and the at least one conductive trace is located between the columns of openings.

6. The integrated circuit device testing system of claim 1 , wherein the circuit board is a multilayer structure that includes a metal core.

7. The integrated circuit device testing system of claim 1 , wherein the circuit board is a multilayer structure comprising a ceramic material.

8. The integrated circuit device testing system of claim 1 , wherein the circuit board comprises anodized aluminum or AlN.

9. The integrated circuit device testing system of claim 1 , further comprising

a load board configured to electrically connect the at least one conductive trace to the controller.

10. The integrated circuit device testing system of claim 1 , wherein the active circuit is located in a load board that is electrically connected to the at least one conductive trace.

11. The system of claim 1 , wherein the at least one conductive trace is electrically connected to the controller or active circuit via a four wire Kelvin connection.

12. The integrated circuit device testing system of claim 1 ,

further comprising a thermal unit configured to heat and/or cool the integrated circuit device based on the detected temperature of the integrated circuit device.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047640, FRAME 0566 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: DELTA DESIGN, INC.
Reel/Frame 066762/0857 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047640 FRAME 0566. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Jan 2, 2019
From: DELTA DESIGN, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 048003/0306 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2018
From: DELTA DESIGN, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047640/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2018
From: TUSTANIWSKYJ, JERRY IHOR
To: DELTA DESIGN, INC.
Reel/Frame 044563/0045 →
Cited By (1)
US 12,704,544