Apparatus for performing modal interval calculations based on decoration configuration

1. Apparatus for calculating a first result modal interval dependent on a first modal interval, each said modal interval defined by first and second endpoints each comprising sign, fraction and exponent bit fields, said apparatus comprising:

a) a first operand register for holding the first and second endpoints of the first modal interval, and for providing a first operand signal specifying the contents of the first modal interval endpoints' fields;

b) a first analysis element for receiving the first operand signal, for creating a first truth table for the first endpoint and a second truth table for the second endpoint, each truth table including a sign bit (S) indicating the sign of the respective endpoint, a not-a-number bit (N) indicating whether the respective endpoint is Not-a-Number, an infinity bit (I) indicating whether the respective endpoint is infinity and a zero bit (Z) indicating whether the respective endpoint is zero;

c) a first logic array for determining a classification from the first and second truth tables, the classification including an empty bit (E) and, optionally, a tracking decoration (T), wherein:

when the first and second truth tables indicate that the first and second endpoints have the same sign and a value of infinity, the empty bit is 1 and the tracking decoration indicates an empty or non-empty restriction;

when the first and second truth tables indicate that one of the first and second endpoints are not-a-number, the empty bit is 1 and the tracking decoration is the NaN decoration field from the not-a-number endpoint;

when the first and second truth tables indicate that both of the first and second endpoints are not-a-number, the empty bit is 1 and the tracking decoration indicates an empty input restriction;

otherwise the empty bit is 0 and the tracking decoration is not used; and,

d) a first computational element receiving the first operand signal and the empty bit value signal, and performing a computation associated with the first computational element using the data encoded in the first operand signal and the empty bit value signal, and providing a result signal encoding the first result modal interval as a result of the computation by the first computational element.

2. The apparatus of claim 1 , wherein the first analysis element creates the first and second truth tables dependent on a preselected exponent field bit configuration in each of the first and second endpoints, and on a preselected fraction field configuration in each of the first and second endpoints.

3. The apparatus of claim 1 adapted for calculating a second result modal interval dependent on the first modal interval and on a second modal interval having the same structure as the first modal interval and having a third endpoint and a fourth endpoint, comprising:

a) a second operand register for holding the third endpoint and the fourth endpoint of the second modal interval, and for providing a second operand signal specifying the contents of the second modal interval's endpoints' fields;

b) a second analysis element for receiving the second operand signal, creating a third truth table for the third endpoint and a fourth truth table for the fourth endpoint;

c) a second logic array for determining a classification from the third and fourth truth tables, the classification including an empty bit (E) and, optionally, a tracking decoration (T), wherein:

when the third and fourth truth tables indicate that the third and fourth endpoints have the same sign and a value of infinity, the empty bit is 1 and the tracking decoration indicates an empty or non-empty restriction;

when the third and fourth truth tables indicate that one of the third and fourth endpoints are not-a-number, the empty bit is 1 and the tracking decoration is the NaN decoration field from the not-a-number endpoint;

when the third and fourth truth tables indicate that both of the third and fourth endpoints are not-a-number, the empty bit is 1 and the tracking decoration indicates an empty input restriction;

otherwise the empty bit is 0 and the tracking decoration is not used;

d) a third logic array for receiving the classifications and generating therefrom first and second multiplexer control signals;

e) at least first and second multiplexers each having a control terminal for receiving respectively the first and second multiplexer control signals at the control terminals thereof, each multiplexer further having first and second data terminals, and each multiplexer gating data present at one of the first and second data input terminals as selected by the multiplexer control signal to create a multiplexer output signal at an output terminal of the multiplexer involved encoding the bit values present at the selected input terminal;

f) connections providing the contents of selected bits in the first and second endpoints to respectively, the first multiplexer's first and second data terminals;

g) connections providing the contents of selected bits in the third and fourth endpoints to respectively, the second multiplexer's first and second data terminals; and,

h) a second computational element for receiving the first and second operands signals, the first and second empty bit value signals, and the first and second multiplexer output terminal signals, and performing a computation associated with the second computational element using the data encoded in the first and second operand signals, the empty bit value signals, and the first and second multiplexer output signals, and providing a second result signal encoding the second result modal interval as a result of the computation by the second computational element.