Unidirectional clock signaling in a high-speed serial link
Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.
1. A method of a master device for transmission of data over a serial link using a unidirectional clock signal, the method comprising:
generating the unidirectional clock signal based on a first clock of the master device;
sending the unidirectional clock signal from a serializer-deserializer (SERDES) of the master device to a SERDES of a slave device that is connected to the serial link, wherein the slave device is configured to generate an intermediate clock signal based on the unidirectional clock signal;
transmitting data from the SERDES of the master device to the SERDES of the slave device over the serial link based on the first clock; and
receiving data from the SERDES of the slave device over the serial link based on the intermediate clock signal.
2. The method of claim 1 , wherein the unidirectional clock is generated to have a same rate as the first clock.
3. The method of claim 1 , wherein the unidirectional clock signal is generated such that a rate of the unidirectional clock signal is a fraction of a rate of the first clock.
4. The method of claim 1 , wherein the unidirectional clock signal is sent over the serial link to the slave device.
5. The method of claim 1 , wherein the unidirectional clock signal is sent over a sideband to the slave device.
6. A method of a slave device for transmission of data over a serial link using a unidirectional clock signal, the method comprising:
receiving the unidirectional clock signal from a serializer-deserializer (SERDES) of a master device at a SERDES of the slave device, wherein the unidirectional clock signal is based on a first clock of the master device;
generating an intermediate clock signal based on the unidirectional clock signal; and
transmitting data from the SERDES of the slave device over the serial link to the SERDES of the master device based on the intermediate clock signal.
7. The method of claim 6 , wherein a rate of the unidirectional clock is the same as a rate of the first clock.
8. The method of claim 6 , wherein a rate of the unidirectional clock signal is a fraction of a rate of the first clock.
9. The method of claim 6 , wherein the unidirectional clock signal is received over a second serial link from the master device.
10. The method of claim 6 , wherein the unidirectional clock signal is received over a sideband from the master device.
11. An apparatus configured to transmit data over a serial link using a unidirectional clock signal, the apparatus comprising:
a master device including
a clock signal generator configured to generate the unidirectional clock signal based on a first clock;
a first transmitter configured to send the unidirectional clock signal from a serializer-deserializer (SERDES) of the master device to a SERDES of a slave device that is connected to the serial link, wherein the slave device is configured to generate an intermediate clock signal based on the unidirectional clock signal;
a second transmitter configured to send data from the SERDES of the master device to the SERDES of the slave device over the serial link based on the first clock; and
a receiver configured to receive data from the from the SERDES of the slave device over the serial link based on the intermediate clock signal.
12. The apparatus of claim 11 , wherein the clock signal generator is configured to generate the unidirectional clock to have a same rate as the first clock.
13. The apparatus of claim 11 , wherein the clock signal generator is configured to generate the unidirectional clock such that a rate of the unidirectional clock signal is a fraction of a rate of the first clock.
14. The apparatus of claim 11 , wherein the first transmitter is configured to transmit the unidirectional clock signal over a second serial link to the slave device.
15. The apparatus of claim 11 , wherein the first transmitter is configured to transmit the unidirectional clock signal over a sideband to the slave device.
16. An apparatus configured to transmit data over a serial link using a unidirectional clock signal, the apparatus comprising:
a slave device including
a receiver of a serializer-deserializer (SERDES) of the slave device, wherein the receiver is configured to receive the unidirectional clock signal from a SERDES of a master device, wherein the unidirectional clock signal is based on a first clock of the master device,
a clock signal generator configured to generate an intermediate clock signal based on the unidirectional clock signal; and
a transmitter configured to transmit data from the SERDES of the slave device over the serial link to the SERDES of the master device based on the intermediate clock signal.
17. The apparatus of claim 16 , wherein a rate of the unidirectional clock is the same as a rate of the first clock.
18. The apparatus of claim 16 , wherein a rate of the unidirectional clock signal is a fraction of a rate of the first clock.
19. The apparatus of claim 16 , wherein the receiver is configured to receive the unidirectional clock signal over a second serial link from the master device.
20. The apparatus of claim 16 , wherein the receiver is configured to receive the unidirectional clock signal over a sideband from the master device.