Semiconductor device with surface insulating film
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.
1. A semiconductor device comprising:
a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion;
a gate trench formed at a surface side of the cell portion;
a gate electrode buried in the gate trench via a gate insulating film; and
a gate finger to make contact with the gate electrode, the gate finger disposed in at least the outer peripheral portion,
wherein the gate trench includes a line-shaped trench that reaches the outer peripheral portion and runs across the gate finger under the gate finger.
2. The semiconductor device according to claim 1 , wherein
the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and
the semiconductor device further comprises a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
3. The semiconductor device according to claim 1 , further comprising a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, wherein
a first part of the surface insulating film on the cell portion has the same thickness as that of a second part of the surface insulating film on the outer peripheral portion.
4. The semiconductor device according to claim 1 , wherein the gate trench includes an inner trench at a portion lateral to which the channel is formed at ON-time, and an outer trench constituted of an extension portion of the inner trench, disposed outside with respect to the inner trench, and
the semiconductor device further includes a second conductivity-type layer formed at side and bottom portions of the outer trench.
5. The semiconductor device according to claim 1 , wherein
the gate trench is selectively formed in a region under the gate finger, and
the semiconductor device further comprises a high-concentration layer of a first conductivity type formed in a semiconductor surface of the semiconductor layer where the gate trench is not formed in the region under the gate finger, containing an impurity at a higher concentration than that of the semiconductor layer.
6. The semiconductor device according to claim 1 , wherein the cell portion includes:
a source region of a first conductivity type disposed in a manner exposed on a surface of the semiconductor layer;
a channel region of a second conductivity type which is disposed in a manner contacting the source region and in which the channel is formed at ON-time;
a drain region of a first conductivity type disposed in a manner contacting the channel region;
a second trench selectively formed in a source portion defined in a manner including the source region in the surface of the semiconductor layer; and
a channel contact region of a second conductivity type selectively disposed at a bottom portion of the second trench, electrically connected with the channel region.
7. The semiconductor device according to claim 1 , wherein the cell portion includes:
a source region of a first conductivity type disposed in a manner exposed on a surface of the semiconductor layer;
a channel region of a second conductivity type which is disposed in a manner contacting the source region and in which the channel is formed at ON-time;
a drain region of a first conductivity type disposed in a manner contacting the channel region;
a second trench selectively formed in a source portion defined in a manner including the source region in the surface of the semiconductor layer;
a trench buried portion buried in the second trench; and
a channel contact region of a second conductivity type selectively disposed at a position higher than that of a bottom portion of the second trench in the source region, electrically connected with the channel region.
8. The semiconductor device according to claim 7 , wherein the trench buried portion consists of an insulating film formed on an inner surface of the second trench and a polysilicon layer buried inside of the insulating film.
9. The semiconductor device according to claim 8 , wherein the insulating film is made of any of SiO 2 , AlON, Al 2 O 3 , SiO 2 /AlON, SiO 2 /AlON/SiO 2 , SiO 2 /SiN, and SiO 2 /SiN/SiO 2 .
10. The semiconductor device according to claim 8 , wherein the insulating film has a SiO 2 film containing nitrogen (N).
11. The semiconductor device according to claim 8 , wherein the insulating film is, at the bottom portion of the second trench, formed to be thicker than a part at a side portion of the second trench.
12. The semiconductor device according to claim 8 , wherein the polysilicon layer is made of n + -type polysilicon.
13. The semiconductor device according to claim 7 , wherein the trench buried portion consists of an insulating layer that fills back the second trench.
14. The semiconductor device according to claim 13 , wherein the insulating layer is made of SiO 2 .
15. The semiconductor device according to claim 14 , wherein the insulating layer is made of SiO 2 containing phosphorus (P) or boron (B).
16. The semiconductor device according to claim 7 , wherein the trench buried portion consists of a polysilicon layer that fills back the second trench.
17. The semiconductor device according to claim 16 , wherein the polysilicon layer is made of p + -type polysilicon.
18. The semiconductor device according to claim 6 , further comprising a second conductivity-type layer formed at the bottom portion and a side portion of the second trench in a manner continuing from the channel region and the channel contact region.
19. The semiconductor device according to claim 1 , wherein the gate electrode includes a base film made of polysilicon formed on an inner surface of the gate trench, and a buried metal containing at least one of Mo, W, Al, Pt, Ni, and Ti buried inside of the base film.
20. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a surface metal layer made of a metal containing copper (Cu) disposed at a surface side of the semiconductor layer.
21. The semiconductor device according to claim 20 , wherein the surface metal layer contains an Al—Cu-based alloy.
22. The semiconductor device according to claim 1 , wherein in the cell portion, unit cells defined in a grid shape by the gate trench are formed in plural numbers.
23. The semiconductor device according to claim 1 , wherein in the cell portion, unit cells defined in a striped shape by the gate trench are formed in plural numbers.
24. The semiconductor device according to claim 1 , wherein the semiconductor layer is made of SiC, GaN, or diamond.
25. The semiconductor device according to claim 3 , wherein the first part and the second part of the surface insulating film have thickness of 5500 Å to 20000 Å.