Microcontroller and electronic control unit
A microcontroller includes two processing blocks that respectively have a Central Processing Unit (CPU) and a peripheral circuit, where an access to the peripheral circuit in each of the processing blocks, that is, to a Read-Only Memory (ROM) or a Pulse Width Modulator (PWM) signal generator, is limited only from the CPU disposed in the same processing block. Thereby a fail-safe functionality of the microcontroller is improved.
1. A microcontroller comprising:
at least two processing blocks provided on one semiconductor chip, each of the processing blocks including a Central Processing Unit (CPU) and a peripheral circuit, wherein the peripheral circuit included in one processing block is not accessible by the CPU included in another processing block;
a shared memory that is accessible from the CPU in each of the at least two processing blocks, wherein the shared memory is part of a random access memory that is directly read accessible and directly write accessible, as memory, by all of the CPUs in the microcontroller;
a plurality of clock feeders each producing a respective clock signal; and
a plurality of switching circuits configured to alternate between feeding the at least two processing blocks one of the respective clock signals and another one of the respective clock signals.
2. The microcontroller of claim 1 further comprising:
a lockstep core that is provided as one of the peripheral circuits.
3. The microcontroller of claim 1 , wherein
each of the processing blocks receives the respective clock signals selectively from normally-operating clock feeders.
4. The microcontroller of claim 3 further comprising:
a clock monitor monitoring an operation of each of the plurality of clock feeders.
5. The microcontroller of claim 3 , wherein
each of the plurality of clock feeders is monitored by an external clock monitor to determine whether an operation of each of the plurality of clock feeders is normal.
6. The microcontroller of claim 1 , wherein
each of the at least two processing blocks receives the respective clock signals from a corresponding clock feeder.
7. The microcontroller of claim 1 , wherein
at least one of the plurality of clock feeders generates the respective clock signals based on an oscillation input from an externally-attached source of oscillation.
8. The microcontroller of claim 7 , wherein
the externally-attached oscillation source is an oscillator.
9. The microcontroller of claim 1 , wherein
at least one of the plurality of clock feeders generates the respective clock signals based on an oscillation input from an internal source of oscillation.
10. The microcontroller of claim 9 , wherein
the internal source of oscillation is a Micro Electro-Mechanical System (MEMS) oscillator.
11. The microcontroller of claim 1 , wherein the shared memory is a random access memory (RAM).
12. An electronic control unit comprising:
the microcontroller of claim 1 , and
a communication line multiplexed for an input of a signal to the microcontroller from a plurality of external controllers, wherein
a drive signal for driving a same actuator is output from each of at least two processing blocks, based on the signal from the plurality of external controllers.
13. The electronic control unit of claim 12 further comprising:
a communication monitor (a) monitoring communication between the plurality of external controllers, and corresponding processing block, and (b) determining whether communication between the plurality of external controllers and the corresponding processing block is normal; and
a processing block selector (a) selecting a normally-operating processing block and (b) switching to the normally-operating processing block for outputting the drive signal for driving the actuator.
14. A microcontroller comprising:
at least two processing blocks provided on one semiconductor chip, each of the processing blocks including a Central Processing Unit (CPU) and a peripheral circuit, wherein the peripheral circuit included in one processing block is not accessible by the CPU included in another processing block; and
a plurality of clock feeders each producing a respective clock signal; and
at least two switching circuits configured to alternate between feeding the at least two processing blocks one of the respective clock signals and another one of the respective clock signals.
15. The microcontroller of claim 14 , further comprising:
a lockstep core that is provided as one of the peripheral circuits.