Processing device with sensitive data access mode

1. A method of protecting sensitive data comprising:

entering, by a processing device, a sensitive data access mode in which sensitive data is accessible;

restricting, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function, and calling, from the sensitive data access mode, the non-secure function; and

entering, by the processing device, a second operating mode to execute the non-secure function, the second operating mode being different from the sensitive data access mode, wherein during the second operating mode the processing device has access to only the one or more accessible address ranges.

2. The method of claim 1 , further comprising storing in the one or more accessible address ranges, by the program running in the sensitive data access mode, input data to be processed during execution of the non-secure function.

3. The method of claim 1 , wherein restricting the one or more accessible address ranges for the non-secure function comprises configuring, in one or more configuration registers of a memory protection circuit, the one or more accessible address ranges.

4. The method of claim 3 , further comprising:

receiving, by the memory protection circuit during execution of the non-secure function, an address to be accessed;

comparing the address to be accessed with the one or more accessible address ranges; and

triggering the memory access only if the address to be accessed is within the one or more accessible address ranges.

5. The method of claim 1 , further comprising defining in a register a stack pointer pointing to call parameters stored in the one or more accessible address ranges and to be used by the non-secure function.

6. The method of claim 1 , further comprising executing the non-secure function in the second operating mode by fetching instruction code from an instruction code memory.

7. The method of claim 6 , wherein the instruction code stored in the instruction code memory is encrypted, the method further comprising decrypting the instruction code.

8. The method of claim 7 , wherein the instruction code is decrypted by a decryption circuit using a first key associated with the second operating mode, and wherein the instruction code memory further stores further instruction code associated with the sensitive operating mode and capable of being decrypted using a second key different to the first key, wherein the decryption circuit is configured to render the second key accessible only while the processing device is in the sensitive data access mode.

9. The method of claim 1 , further comprising returning to the sensitive data access mode upon termination of the non-secure function.

10. The method of claim 9 , wherein the termination of the non-secure function is triggered by an event external to the processing device.

11. The method of claim 9 , wherein the termination of the non-secure function is triggered by at least one of:

the detection, by a memory protection circuit, of an attempt to access an address outside the one or more accessible address ranges;

the detection of an attempt to access a forbidden peripheral device;

the detection of an attempt to access a forbidden register;

the detection of an attempt to access an unknown or forbidden instruction; and

the detection of an interrupt generated by a peripheral device.

12. A computing system comprising:

a processing device capable of operating in a sensitive data access mode in which sensitive data is accessible, and in a second operating mode, the second operating mode being different from the sensitive data access mode, the processing device being configured to:

restrict, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function;

call, from the sensitive data access mode, the non-secure function; and

enter the second operating mode to execute the non-secure function during which the processing device has access to only the one or more accessible address ranges.

13. The computing system of claim 12 , further comprising a decryption circuit configured to decrypt instruction code of the non-secure function prior to its execution by the processing device.

14. The computing system of claim 12 , further comprising:

an instruction code memory storing the instruction code and further instruction code associated with the sensitive operating mode; and

a decryption circuit adapted to decrypt the instruction code using a first key associated with the second operating mode, and decrypt the further instruction code using a second key different to the first key, wherein the decryption circuit is configured to render the second key accessible only while the processing device is in the sensitive data access mode.

15. The computing system of claim 12 , wherein the processing device is configured to terminate the non-secure function in response to an interrupt generated in response to the detection of one or more of:

an attempt to access an address outside the one or more accessible address ranges;

an attempt to access a forbidden peripheral device;

an attempt to access a forbidden register;

an attempt to access an unknown or forbidden instruction; and

an interrupt generated by a peripheral device.