IP Library Granted Patent US 10,234,626
Granted Patent B2
US 10,234,626 · App. 15/426,366 · Granted Mar 19, 2019

Stepped optical bridge for connecting semiconductor waveguides

Inventor: Damien Lambert (Los Altos, CA)
Assignee: Skorpios Technologies, Inc.
G02B6/12002G02B6/122G02B6/12004G02B6/12007G02B6/136H01S5/021H01S5/0202H01S5/026H01S5/028H01S5/02252H01S5/22H01S5/3013H01S5/343H01S5/4025H01S5/4087H04B10/505H04J14/02G02B2006/12061G02B2006/12104G02B2006/12121G02B2006/12142G02B2006/12147
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Quick Facts
Patent No.
US 10,234,626
App. No.
15/426,366
Granted
Mar 19, 2019
Kind
B2
Abstract

A photonic device includes a semiconductor wafer having a waveguide formed therein. An end of the waveguide includes a step. The photonic device further includes a semiconductor chip bonded to the semiconductor wafer and having an active region, and a waveguide coupler disposed in a gap between a sidewall of the semiconductor chip and the end of the waveguide. The waveguide coupler includes an optical bridge that has a first end and a second end opposing the first end. The first end of the optical bridge is interfaced with a facet of the active region of the semiconductor chip. The second end of the optical bridge is interfaced with the end of waveguide, and has a portion thereof disposed over the step at the end of the waveguide.

Claims (59)

1. A photonic device comprising:

a semiconductor wafer comprising:

a base layer;

a first insulating layer disposed over a surface of the base layer;

a device layer disposed over the first insulating layer; and

a waveguide formed in the device layer;

wherein the semiconductor wafer comprises walls defining a recess in the device layer and the first insulating layer, the recess exposing a portion of the surface of the base layer and an end of the waveguide; and

wherein the end of the waveguide comprises a first step having a first length and a first height, the first height being less than a thickness of the waveguide;

a semiconductor chip bonded to the surface of the base layer of the semiconductor wafer, wherein:

the semiconductor chip comprises an active region;

a facet of the active region is exposed at a sidewall of the semiconductor chip; and

there is a gap between the sidewall of the semiconductor chip and one of the walls of the semiconductor wafer defining the recess; and

a waveguide coupler disposed in the gap, the waveguide coupler comprising:

a second insulating layer disposed over the surface of the base layer of the semiconductor wafer; and

an optical bridge disposed over the second insulating layer, wherein:

the optical bridge has a first end and a second end opposing the first end;

the first end of the optical bridge is interfaced with the facet of the active region; and

the second end of the optical bridge has a second step having a second length and a second height, the second height being less than a thickness of the optical bridge, and the second step is disposed over the first step of the waveguide.

2. The photonic device of claim 1 , wherein the first height of the first step ranges from about 5% to about 95% of the thickness of the waveguide.

3. The photonic device of claim 2 , wherein the first height of the first step ranges from about 10% to about 85%, or from about 20% to about 75%, or from about 30% to about 65%, or from about 40% to about 55%, of the thickness of the waveguide.

4. The photonic device of claim 1 , wherein the first length of the first step ranges from about 0.1 μm to about 50 μm.

5. The photonic device of claim 4 , wherein the first length of the first step ranges from about 0.5 μm to about 50 μm, or from about 1 μm to about 50 μm, or from about 5 μm to about 50 μm.

6. The photonic device of claim 1 , wherein the base layer of the semiconductor wafer comprises silicon.

7. The photonic device of claim 6 , wherein the semiconductor chip comprises a III-V material.

8. The photonic device of claim 7 , wherein the active region comprises a multiple-quantum-well (MQW) structure.

9. The photonic device of claim 1 , further comprising:

a third insulating layer disposed over the waveguide.

10. The photonic device of claim 9 , wherein:

the base layer of the semiconductor wafer comprises silicon;

the waveguide comprises crystalline silicon; and

the first insulating layer, the second insulating layer, and the third insulating layer comprise silicon oxide.

11. The photonic device of claim 10 , wherein the optical bridge comprises amorphous silicon.

12. The photonic device of claim 1 , wherein the waveguide has a first refractive index, and the optical bridge has a second refractive index different from the first refractive index.

13. A method for fabricating a photonic device, the method comprising:

providing a semiconductor wafer, the semiconductor wafer comprising:

a base layer;

a first insulating layer disposed over a surface of the base layer;

a device layer disposed over the first insulating layer; and

a waveguide formed in the device layer;

performing etching to form a recess in the device layer and the first insulating layer, wherein:

the recess exposes a portion of the surface of the base layer; and

the recess has a sidewall exposing an end of the waveguide;

bonding a semiconductor chip to the exposed portion of the surface of the base layer, wherein:

the semiconductor chip comprises an active region;

a facet of the active region is exposed at a sidewall of the semiconductor chip; and

there is a gap between the sidewall of the semiconductor chip and the sidewall of the recess;

forming a second insulating layer in the gap;

performing etching to remove a portion of the waveguide to form a first step at the end of the waveguide; and

forming an optical bridge over the second insulating layer, wherein:

the optical bridge has a first end and a second end opposing the first end;

the first end of the optical bridge is interfaced with the facet of the active region; and

the second end of the optical bridge has a second step disposed over the first step at the end of the waveguide.

14. The method of claim 13 , wherein the first step has a height ranging from about 5% to about 95% of the thickness of the waveguide.

15. The method of claim 14 , wherein the first step has a height ranging from about 10% to about 85%, or from about 20% to about 75%, or from about 30% to about 65%, or from about 40% to about 55%, of the thickness of the waveguide.

16. The method of claim 13 , wherein the first step has a length ranging from about 0.1 μm to about 50 μm.

17. The method of claim 16 , wherein the first step has a length ranging from about 0.5 μm to about 50 μm, or from about 1 μm to about 50 μm, or from about 5 μm to about 50 μm.

18. The method of claim 13 , wherein the base layer of the semiconductor wafer comprises silicon.

19. The method of claim 18 , wherein the semiconductor chip comprises a III-V material.

20. The method of claim 19 , wherein the active region comprises a multiple-quantum-well (MQW) structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 043926/0762 →
NUNC PRO TUNC ASSIGNMENT Recorded Sep 22, 2017
From: LAMBERT, DAMIEN
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 043669/0045 →
NUNC PRO TUNC ASSIGNMENT Recorded Sep 21, 2017
From: LAMBERT, DAMIEN
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 043658/0234 →
Continuity (4)
Provisional Application 62292636 · Feb 8, 2016
Provisional Application 62292675 · Feb 8, 2016
Provisional Application 62292633 · Feb 8, 2016
Related Publication 20170227709A1 · Aug 10, 2017