Two-transistor SRAM semiconductor structure and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
1. The semiconductor structure for a pair of cross-coupled PNP and NPN bipolar transistors comprising:
a first conductivity type semiconductor substrate having an upper surface;
an isolation region extending into the substrate from the upper surface defining a pocket of first conductivity type semiconductor material, the pocket having an upper surface and extending to a buried layer of opposite conductivity type at a bottom of the pocket;
a shallow well region of opposite conductivity type extending from the upper surface into the pocket over a first portion of the pocket, but not extending to the buried layer;
a first field effect transistor gate and a second field effect transistor gate disposed at least partly over the first portion, and a third field effect transistor gate disposed at least partly over a second portion of the pocket, the second portion of the pocket being adjacent to the first portion of the pocket;
a first region of first conductivity type disposed on a first side of the first gate;
a second region of first conductivity type disposed on an opposing side of the first gate and adjacent to the second gate;
a third region of opposite conductivity type disposed on a first side of the third gate and also adjacent to the second gate;
a fourth region of opposite conductivity type disposed on an opposing side of the third gate, and further including:
a first electrical connection to the first region;
a second electrical connection to the second region;
a third electrical connection to the third region; and
a fourth electrical connection to the fourth region.
2. The semiconductor structure as in claim 1 wherein the first conductivity type is P conductivity type and the opposite conductivity type is N conductivity type.
3. The semiconductor structure as in claim 1 wherein:
the first, second, and third field effect transistor gates comprise an underlying layer of insulating material and an overlying layer of conductive material; and
the first, second and third field effect transistor gates are disposed on the substrate during a same process that other field effect transistor gates are formed on the semiconductor structure.
4. The semiconductor structure as in claim 1 wherein the semiconductor structure comprises a static random access memory (SRAM) cell.
5. The semiconductor structure as in claim 4 wherein the second electrical connection and the third electrical connection comprise array lines of an SRAM memory.
6. The semiconductor structure as in claim 5 wherein:
the second electrical connection comprises a word line; and
the third electrical connection comprises a bit line.
7. The semiconductor structure as in claim 6 wherein the buried layer extends under the isolation region to provide a bit line to other SRAM cells on the semiconductor substrate.
8. The semiconductor structure as in claim 4 further comprising a fifth electrical connection to a selected one of the first gate and the third gate to enable short-circuiting doped regions adjacent the selected one of the first gate and the third gate together.
9. The semiconductor structure as in claim 8 wherein the fifth electrical connection is connected to a first write assist line.
10. The semiconductor structure as in claim 9 further comprising a sixth electrical connection provided to a non-selected one of the first gate and the third gate to enable short circuiting of the doped regions adjacent the non-selected gate together.
11. The semiconductor structure as in claim 9 wherein the sixth electrical connection is connected to a second write assist line.