Six-transistor SRAM semiconductor structures and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
1. A semiconductor structure for a cross-coupled PNP and NPN bipolar transistors and an adjoining access transistor comprising:
a first conductivity type semiconductor substrate having an upper surface;
an isolation region extending into the substrate from the upper surface defining first and second adjoining pockets of first conductivity type semiconductor material, each of the first and second pockets having an upper surface and extending to a buried layer of opposite conductivity type at a bottom of each pocket;
in the first pocket:
a shallow well region of opposite conductivity type extending from the upper surface into the pocket over a first portion of the pocket, but not extending over a second portion of the pocket and not extending to the buried layer;
a first field effect transistor gate disposed over some of the first portion and some of the second portion;
a second field effect transistor gate spaced apart from the first field effect transistor gate, the second field effect transistor gate being disposed only over some of the first portion;
first and second regions of first conductivity type disposed on opposing sides of the first gate and a first side of the second field effect transistor gate;
a first region of opposite conductivity type disposed on an opposing side of the second gate;
in the second pocket:
an access transistor coupled to the cross-coupled PNP and NPN bipolar transistors; and
electrical connections to each of the first and second regions of first conductivity type disposed on opposing sides of the first gate and the first side of the second field effect transistor gate and to the first region of opposite conductivity type on the opposing side of the second gate.
2. A semiconductor structure as in claim 1 wherein the access transistor comprises a field effect transistor comprising:
a third field effect transistor gate disposed over some of the second pocket; and
second and third regions of opposite conductivity type disposed on opposing sides of the third field effect transistor gate.
3. A semiconductor structure as in claim 2 further comprising:
a word line connected to the third field effect transistor gate;
a bit line connected to one of the second and third regions of opposite conductivity type; and
an electrical connection is provided between the other of the second and third regions of opposite conductivity type and the first region of opposite conductivity type.
4. A semiconductor structure as in claim 1 wherein the access transistor comprises a bipolar transistor comprising:
fourth and fifth field effect transistor gates disposed over spaced apart regions of the second pocket;
a third region of first conductivity disposed between the fourth and fifth field effect transistor gates; and
fourth and fifth regions of opposite conductivity type disposed on opposing sides of the fourth and fifth field effect transistor gates, the fifth region extending into the substrate to contact the buried layer.
5. A semiconductor structure as in claim 4 further comprising:
a word line connected to the third region of first conductivity disposed between the fourth and fifth field effect transistor gates;
a bit line connected to the fifth region of opposite conductivity type; and
an electrical connection between the fourth region of opposite conductivity type and the first region of opposite conductivity type.