Methods of reading and writing data in a thyristor random access memory
A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
1. An integrated circuit comprising:
a plurality of parallel word lines in a first direction and a plurality of parallel bit lines in a second direction perpendicular to the first direction;
a plurality of memory cells, each memory cell having only one thyristor, the thyristor connected between one of the plurality of word lines and one of the plurality of bit lines and holding a logic state corresponding to whether the thyristor is on or off, the thyristor of each memory cell comprises an anode connected to a word line and a cathode connected to a bit line;
a sense amplifier having a first input terminal connected to a first one of the plurality of bit lines, the first one of the plurality of bit lines connected to a plurality of selectable memory cells holding data, a second input terminal connected to a second one of the plurality of bit lines, the second one of the plurality of bit lines acting as a reference bit line, and an output terminal reflecting a comparative voltage of the first one and the second one of the plurality of bit lines; and
a current generator connected to the first one of the plurality of bit lines or to the second one of the plurality of bit lines, the current generator providing a current so as to differentiate pre-charge voltages on the first one and second one of the plurality of bit lines during an operation to read one of the plurality of selectable memory cells holding data, the current having a magnitude less than the magnitude of a current through the thyristor of a selected memory cell in the on state;
whereby a logic state of a selected memory cell is read by the output of the sense amplifier.
2. The method of claim 1 wherein the current generator is connected to the first one of the plurality of bit lines and operates as a current sink to lower the voltage of the first one bit line whereby in a read operation the first one and the second one of the plurality of bit lines are precharged.
3. The method of claim 2 wherein the current generator provides a current having a magnitude about one-half the magnitude of the current through the thyristor of the selected memory cell in the on state.
4. An integrated circuit comprising:
a plurality of parallel word lines in a first direction and a plurality of parallel bit lines in a second direction perpendicular to the first direction;
a plurality of memory cells, each memory cell having only one thyristor, the thyristor connected between one of the plurality of word lines and one of the plurality of bit lines and holding a logic state corresponding to whether the thyristor is on or off, the thyristor of each memory cell comprises a cathode connected to a bit line and an anode connected to a word line;
a sense amplifier having a first input terminal connected to a first one of the plurality of bit lines, the first one of the plurality of bit lines connected to a plurality of selectable memory cells holding data, a second input terminal connected to a second one of the plurality of bit lines, the second one of the plurality of bit lines acting as a reference bit line, and an output terminal reflecting a comparative voltage of the first one and the second one of the plurality of bit lines; and
a current generator connected to the first one of the plurality of bit lines or to the second one of the plurality of bit lines, the current generator providing a current so as to differentiate pre-charge voltages on the first one and second one of the plurality of bit lines during an operation to read one of the plurality of selectable memory cells holding data, the current having a magnitude less than the magnitude of a current through the thyristor of a selected memory cell in the on state;
whereby a logic state of a selected memory cell is read by the output of the sense amplifier.
5. The method of claim 4 wherein the current generator is connected to the second one of the plurality of bit lines and operates as a current source to raise the voltage of the second one bit line.
6. The method of claim 5 wherein the current generator provides a current having a magnitude about one-half the magnitude of the current through the thyristor of the selected memory cell in the on state.