Superlattice memory and crosspoint memory device
View Patent ↗According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.
1. A memory device comprising:
a resistance change layer comprising a first chalcogenide layer and a second chalcogenide layer having a composition different from the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and
a semiconductor layer of a first conductivity type provided on one of main surfaces of the resistance change layer, wherein
the first chalcogenide layer is of a second conductivity type, and
the first chalcogenide layer directly contacts the semiconductor layer.
2. The device of claim 1 , wherein:
the first chalcogenide layer includes Sb, and the second chalcogenide layer includes Ge.
3. The device of claim 1 , wherein:
the first chalcogenide layer is an Sb 2 Te 3 layer, and the second chalcogenide layer is a GeTe layer; and
the Sb 2 Te 3 layer is provided on the semiconductor layer.
4. The device of claim 1 , wherein the semiconductor layer is amorphous silicon, poly-Ge, or InGaZnO.
5. The device of claim 1 , wherein:
the semiconductor layer is of an n-type, and the first chalcogenide layer is of a p-type; and
a pn junction diode is constituted of the semiconductor layer and the first chalcogenide layer.
6. The device of claim 1 , wherein the resistance change layer and the semiconductor layer are provided in a form of a pillar.
7. A memory device comprising:
a resistance change layer comprising a first chalcogenide layer and a second chalcogenide layer having a composition different from the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure;
a first electrode provided at a main surface of the resistance change layer on one side with respect to a layer-stacking direction;
a second electrode provided at another main surface of the resistance change layer on the other side with respect to the layer-stacking direction; and
a semiconductor layer of a first conductivity type provided between the first or the second electrode and the resistance change layer, wherein
the first chaleogenide layer is of a second conductivity type, and
the first chalcogenide layer directly contacts the semiconductor layer.
8. The device of claim 7 , wherein:
the first chalcogenide layer includes Sb, and the second chalcogenide layer includes Ge.
9. The device of claim 7 , wherein:
the first chalcogenide layer is an Sb 2 Te 3 layer, and the second chalcogenide layer is a GeTe layer; and
the Sb 2 Te 3 layer is provided on the semiconductor layer.
10. The device of claim 7 , wherein the semiconductor layer is amorphous silicon, poly-Ge, or InGaZnO.
11. The device of claim 7 , wherein:
the semiconductor layer is of an n-type, and the first chalcogenide layer is of a p-type; and
a pn junction diode is constituted of the semiconductor layer and the first chalcogenide layer.
12. The device of claim 7 , wherein the resistance change layer and the semiconductor layer are provided like a pillar.
13. A memory device comprising:
a plurality of first lines;
a plurality of second lines extending in a direction crossing to the first lines;
a superlattice memory cell arranged at each intersection of the first line and the second line, the superlattice memory cell comprising a first chalcogenide layer, and a second chalcogenide layer having a composition different from the first chalcogenide layer which are stacked alternately; and
a semiconductor layer of a first conductivity type provided between the first line or the second line and the superlattice memory cell, wherein
the first chalcogenide layer is of a second conductivity type and
the first chalcogenide layer directly contacts the semiconductor layer.
14. The device of claim 13 , wherein:
the first chalcogenide layer includes Sb, and the second chalcogenide layer includes Ge.
15. The device of claim 13 , wherein:
the first chalcogenide layer is an Sb 2 Te 3 layer, and the second chalcogenide layer is a GeTe layer; and
the Sb 2 Te 3 layer is provided on the semiconductor layer.
16. The device of claim 13 , wherein the semiconductor layer is amorphous silicon, poly-Ge, or InGaZnO.
17. The device of claim 13 , wherein:
the semiconductor layer is of an n-type, and the first chalcogenide layer is of a p-type; and
a pn junction diode is constituted of the semiconductor layer and the first chalcogenide layer.
18. The device of claim 13 , wherein the first chalcogenide layer, the second chalcogenide layer, and the semiconductor layer are provided in a form of a pillar.
19. The device of claim 13 , wherein the first chalcogenide layer and the second chalcogenide layer are provided to be continuous over the superlattice memory cells, and the semiconductor layer is provided in a form of a pillar.
20. The device of claim 13 , wherein the first chalcogenide layer, the second chalcogenide layer, and the semiconductor layer are provided to be continuous over the superlattice memory cells.