Split gate charge trapping memory cells having different select gate and memory gate heights
A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.
1. A memory device comprising:
a first dielectric disposed over a substrate, the first dielectric comprising a silicon nitride charge trapping layer between two layers of silicon oxide;
a memory gate disposed over the first dielectric, the memory gate having a first memory gate sidewall, and a first gate height which is a maximum height of a top surface of the memory gate above the substrate;
a second dielectric disposed over the substrate and adjacent to the first memory gate sidewall, the second dielectric having a first vertical portion adjacent to the first memory gate sidewall and a horizontal portion adjacent to the first vertical portion, the second dielectric consisting of a single layer of a dielectric material; and
a select gate disposed over the horizontal portion of the second dielectric having a first select gate sidewall adjacent to the first vertical portion, and having a second gate height,
wherein the second gate height is greater than the first gate height, wherein the first select gate sidewall and the first vertical portion of the second dielectric extend above the top surface of the memory gate, and wherein the memory gate and the second select gate comprise planar top surfaces parallel to a surface of the substrate.
2. The memory device of claim 1 , further comprising a first doped region in the substrate adjacent to a second memory gate sidewall through which the memory device is coupled to a source line (SL), and a second doped region in the substrate adjacent to a second select gate sidewall through which the memory device is coupled to a bit line (BL).
3. A memory device comprising:
a memory gate disposed over a first dielectric on a surface of a substrate, the memory gate having a first memory gate sidewall, and a second memory gate sidewall;
a second dielectric having a first vertical portion disposed adjacent to the first memory gate sidewall, a second vertical portion disposed adjacent to the second memory gate sidewall and a horizontal portion disposed over the substrate adjacent to the first and second vertical portions;
a first select gate disposed on the horizontal portion adjacent to the first vertical portion disposed adjacent to the first memory gate sidewall; and
a second select gate disposed on the horizontal portion adjacent to the second vertical portion disposed adjacent to the first memory gate sidewall,
wherein the first and second select gates and the first and second vertical portions extend above a top surface of the memory gate, and wherein the memory gate, and the first and second select gates comprise planar top surfaces parallel to the surface of the substrate.
4. The memory device of claim 3 , wherein the first and second vertical portions and the horizontal portion of the second dielectric have a uniform thickness.
5. The memory device of claim 4 , wherein the first and second vertical portions and the horizontal portion of the second dielectric comprise a single layer of a single material.
6. A memory device comprising:
a plurality of split gate memory cells, each split gate memory cell comprising:
a memory gate overlying a charge trapping dielectric on a substrate, the memory gate comprising polysilicon and including a first sidewall extending vertically from a surface of the substrate and a planar top surface at a first gate height above the surface of the substrate;
a dielectric layer of a single dielectric material having a vertical portion abutting the first sidewall of the memory gate and a horizontal portion formed on the surface of the substrate adjacent thereto, the vertical portion the and horizontal portion being contiguous and having a uniform thickness; and
a select gate overlying the horizontal portion, the select gate having a first sidewall extending vertically from the horizontal portion of the dielectric layer and abutting the vertical portion, and a planar top surface at a second gate height above the surface of the substrate,
wherein the second gate height is greater than the first gate height, and the first sidewall of the select gate and the vertical portion of the dielectric layer extend above the planar top surface of the memory gate.
7. The memory device of claim 6 wherein each split gate memory cell further comprises a doped source region in the substrate adjacent to a second sidewall of the memory gate through which the split gate memory cell is coupled to a source line in the memory device, and a doped drain region in the substrate adjacent to a second sidewall of the select gate through which the split gate memory cell is coupled to a bit line in the memory device.
8. The memory device of claim 7 wherein the doped drain region of a first one of the plurality of split gate memory cells is contiguous and shared with the doped drain region of adjacent second one of the plurality of split gate memory cells.
9. The memory device of claim 6 wherein the charge trapping dielectric is a multilayer dielectric comprising an ONO stack.
10. The memory device of claim 6 wherein the charge trapping dielectric extends completely under and only under the memory gate.
11. The memory device of claim 6 wherein the memory gate comprises a gate length substantially equal to that of the select gate.
12. The memory device of claim 6 wherein the memory gate comprises a gate length greater than a gate length of the select gate.