Circuit for low power, radiation hard logic cell
View Patent ↗This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.
1. An integrated circuit with three input signals, D, Db, and CK, whereby Db is the complement (inverse) of D, implementing a clocked latch function, consisting of 12 MOSFET devices connected between a higher voltage level (VDD) and a lower voltage level (VSS), consisting of:
a) A first p-type MOSFET with its source connected to VDD, its drain connected to a circuit node denoted nm, and its gate connected to a circuit node denoted nmb,
a second p-type MOSFET with its source connected to VDD, its drain connected to a circuit node denoted pp0, and its gate connected to Db,
a third p-type MOSFET with its source connected to the node pp0 and its drain connected to the circuit node nm, and its gate connected to CK,
a fourth p-type MOSFET with its source connected to VDD, its drain connected to the circuit node nmb, and its gate connected to the circuit node nm,
a fifth p-type MOSFET with its source connected to VDD, its drain connected to a circuit node denoted pp1, and its gate connected to D,
a sixth p-type MOSFET with its source connected to the node pp1, its drain connected to the circuit node nmb, and its gate connected to CK,
a first n-type MOSFET with its source connected to VSS, its drain connected to a circuit node denoted nn0, and its gate connected to the circuit node nmb,
a second n-type MOSFET with its source connected to the circuit node nn0, its drain connected to the circuit node nm, and its gate connected to Db,
a third n-type MOSFET with its source connected to the circuit node nn0, its drain connected to the circuit node nm, and its gate connected to CK,
a fourth n-type MOSFET with its source connected to VSS, its drain connected to a circuit node denoted nn1, and its gate connected to the circuit node nm,
a fifth n-type MOSFET with its source connected to the circuit node nn1, its drain connected to the circuit node nmb, and its gate connected to D,
a sixth n-type MOSFET with its source connected to the circuit node nn1, its drain connected to the circuit node nmb, and its gate connected to CK.
2. An integrated circuit with three input signals, D, Db, and CK, whereby Db is the complement (inverse) of D, implementing a clocked latch function, consisting of 12 MOSFET devices connected between a higher voltage level (VDD) and a lower voltage level (VSS), consisting of:
a) A first p-type MOSFET with its source connected to VDD, its drain connected to a circuit node denoted pp0, and its gate connected to a circuit node denoted nmb,
a second p-type MOSFET with its source connected to pp0, its drain connected to a circuit node denoted nm, and its gate connected to Db,
a third p-type MOSFET with its source connected to the node pp0 and its drain connected to the circuit node nm, and its gate connected to CK,
a fourth p-type MOSFET with its source connected to VDD, its drain connected to a circuit node denoted pp1, and its gate connected to the circuit node nm,
a fifth p-type MOSFET with its source connected to pp1, its drain connected to the circuit node nmb, and its gate connected to D,
a sixth p-type MOSFET with its source connected to the node pp1, its drain connected to the circuit node nmb, and its gate connected to CK,
a first n-type MOSFET with its source connected to VSS, its drain connected to the circuit node nm, and its gate connected to the circuit node nmb,
a second n-type MOSFET with its source connected to VSS, its drain connected to a circuit node denoted nn0, and its gate connected to Db,
a third n-type MOSFET with its source connected to the circuit node nn0, its drain connected to the circuit node nm, and its gate connected to CK,
a fourth n-type MOSFET with its source connected to VSS, its drain connected to the circuit node nmb, and its gate connected to the circuit node nm,
a fifth n-type MOSFET with its source connected to VSS, its drain connected to a circuit node denoted nn1, and its gate connected to D,
a sixth n-type MOSFET with its source connected to the circuit node nn1, its drain connected to the circuit node nmb, and its gate connected to CK.