IP Library Granted Patent US 11,373,990
Granted Patent B2
US 11,373,990 · App. 15/431,528 · Granted Jun 28, 2022

Semiconductor device and method of stacking semiconductor die for system-level ESD protection

Inventors: Changjun Huang (Oak Park, CA); Jonathan Clark (Camarillo, CA)
Assignee: Semtech Corporation
H01L25/50H01L21/76898H01L23/49575H01L23/60H01L24/13H01L24/14H01L24/16H01L24/81H01L24/94H01L24/97H01L25/0657H01L21/304H01L21/561H01L21/78H01L23/295H01L23/3121H01L23/3171H01L24/03H01L24/05H01L24/11H01L24/17H01L24/29H01L24/32H01L24/45H01L24/48H01L24/73H01L24/80H01L24/85H01L27/0255H01L2224/0345H01L2224/03452H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/04042H01L2224/05009H01L2224/0557H01L2224/0558H01L2224/05548H01L2224/05568H01L2224/05571H01L2224/05573H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/06181H01L2224/08146H01L2224/08148H01L2224/1132H01L2224/1134H01L2224/1145H01L2224/11334H01L2224/11462H01L2224/11464H01L2224/11849H01L2224/11901H01L2224/13025H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/14181H01L2224/16146H01L2224/16147H01L2224/16227H01L2224/16245H01L2224/17181H01L2224/2929H01L2224/32145H01L2224/32245H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/4847H01L2224/48091H01L2224/48145H01L2224/48247H01L2224/48463H01L2224/48465H01L2224/73253H01L2224/73257H01L2224/8082H01L2224/80203H01L2224/80895H01L2224/8182H01L2224/81203H01L2224/81815H01L2224/85203H01L2224/85205H01L2224/94H01L2224/97H01L2225/0651H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06565H01L2924/1033H01L2924/10252H01L2924/10253H01L2924/10272H01L2924/10322H01L2924/10324H01L2924/10329H01L2924/10335H01L2924/1203H01L2924/13091H01L2924/141H01L2924/143H01L2924/1433H01L2924/1434H01L2924/1461
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Quick Facts
Patent No.
US 11,373,990
App. No.
15/431,528
Granted
Jun 28, 2022
Kind
B2
Abstract

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

Claims (49)

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die comprising a first transient voltage suppression (TVS) diode;

disposing a second semiconductor die comprising a second TVS diode over the first semiconductor die;

disposing the first semiconductor die and the second semiconductor die over a leadframe, wherein a first terminal of the first TVS diode is directly electrically coupled to a first terminal of the second TVS diode, and wherein a second terminal of the first TVS diode is directly electrically coupled to a second terminal of the second TVS diode;

depositing an encapsulant over the first semiconductor die, the second semiconductor die, and the leadframe; and

singulating through the encapsulant to form a semiconductor package, wherein the semiconductor package is configured to protect a separate semiconductor package from a transient electrical signal by routing the transient electrical signal through the first TVS diode and the second TVS diode in parallel.

2. The method of claim 1 , further including bonding the first semiconductor die to the leadframe using a conductive bump.

3. The method of claim 1 , further including bonding the first semiconductor die to the second semiconductor die using a conductive bump.

4. The method of claim 1 , further including bonding the first semiconductor die to the second semiconductor die using thermocompression.

5. The method of claim 1 , further including:

forming a conductive via in the first semiconductor die;

backgrinding the first semiconductor die to expose the conductive via; and

disposing the second semiconductor die over the first semiconductor die with a contact pad of the second semiconductor die aligned with the conductive via.

6. A method of making a semiconductor device, comprising:

providing a first semiconductor die including a first discrete transient voltage suppression (TVS) diode;

providing a second semiconductor die including a second discrete TVS diode;

disposing the second semiconductor die over the first semiconductor die with the first discrete TVS diode and the second discrete TVS diode electrically coupled in parallel;

disposing the first semiconductor die and the second semiconductor die over a substrate, wherein the first and the second semiconductor die are configured to semiconductor die protect a separate semiconductor package from an electrical transient when the separate semiconductor package is coupled to the first semiconductor die and the second semiconductor die through the substrate; and

depositing an encapsulant over the first semiconductor die and the second semiconductor die.

7. The method of claim 6 , wherein the substrate includes a leadframe.

8. The method of claim 6 , further including disposing a third semiconductor die over the first semiconductor die and the second semiconductor die.

9. The method of claim 6 , wherein the semiconductor device has exactly two electrical terminals.

10. A method of making a semiconductor device, comprising:

providing a first semiconductor die comprising a first discrete transient voltage suppression (TVS) diode;

providing a second semiconductor die comprising a second discrete TVS diode; and

disposing the first semiconductor die and the second semiconductor die over a leadframe with the first discrete TVS diode and the second discrete TVS diode coupled in parallel, wherein the first discrete TVS diode and the second discrete TVS diode are configured to protect a separate semiconductor package from a transient electrical signal by coupling the separate semiconductor package to the leadframe.

11. The method of claim 10 , further including:

providing a third semiconductor die comprising a third discrete TVS diode; and

disposing the third semiconductor die over the first semiconductor die and the second semiconductor die with the third discrete TVS diode electrically coupled in parallel with the first discrete TVS diode and the second discrete TVS diode.

12. The method of claim 10 , further including:

forming a first conductive via through the first semiconductor die;

forming a second conductive via through the second semiconductor die; and

connecting the first conductive via to the second conductive via.

13. The method of claim 10 , further including depositing an encapsulant over the first semiconductor die, the second semiconductor die, and the leadframe.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor die comprising a first discrete transient voltage suppression (TVS) diode;

providing a second semiconductor die comprising a second discrete TVS diode;

disposing the second semiconductor die over the first semiconductor die with the first discrete TVS diode and the second discrete TVS diode electrically coupled in parallel; and

depositing an encapsulant over the first semiconductor die and the second semiconductor die.

15. The method of claim 14 , wherein the semiconductor device has exactly two electrical terminals.

16. The method of claim 14 , wherein the semiconductor device is configured to protect a separate semiconductor package from a transient voltage.

17. The method of claim 14 , further including:

providing a third semiconductor die comprising a third discrete TVS diode; and

disposing the third semiconductor die over the first semiconductor die and the second semiconductor die with the third discrete TVS diode electrically coupled in parallel with the first discrete TVS diode and the second discrete TVS diode.

18. The method of claim 14 , further including:

forming a first conductive via through the first semiconductor die;

forming a second conductive via through the second semiconductor die; and

connecting the first conductive via to the second conductive via.

19. The method of claim 1 , wherein the semiconductor package has exactly two terminals.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jul 8, 2026
From: JPMORGAN CHASE BANK, N.A.
To: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
Reel/Frame 075211/0699 →
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (043070/0051) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0735 →
SECURITY INTEREST Recorded Jul 21, 2017
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043070/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2017
From: HUANG, CHANGJUN; CLARK, JONATHAN
To: SEMTECH CORPORATION
Reel/Frame 041243/0153 →
Continuity (2)
Provisional Application 62301045 · Feb 29, 2016
Related Publication 20170250172A1 · Aug 31, 2017