Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain
Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.
1. A vertical field effect transistor (FET) device having gate and source or drain features, the device comprising:
a fin formed in a substrate;
wherein the fin includes an upper fin region and a lower base region;
wherein the upper fin region includes an upper fin width dimension;
wherein the lower base region includes an upper surface and a base width dimension;
wherein the base width dimension is greater than the upper fin width dimension;
wherein the lower base region further comprise a portion of a source or a drain region;
wherein the source or the drain region is configured to extend beyond the lower base region into a portion of the substrate;
wherein the source or the drain region is communicatively coupled to the upper fin region;
a trench formed in the source or the drain region;
wherein at least a portion of the trench comprises a substantially planar upper surface of the lower base region;
wherein the substantially planer upper surface of the lower base region is formed at an angle with respect to a major surface of the substrate;
a dielectric region formed in the trench; and
a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region comprises at least a portion of the dielectric region.
2. The device of claim 1 , wherein the angle comprises greater than zero degrees and less than ninety degrees.
3. The device of claim 1 , wherein the dielectric region comprises a low-k material.
4. The device of claim 1 , wherein at least a portion of the source or the drain region is formed from the lower base region.
5. A vertical field effect transistor (FET) device having gate and source or drain features, the device comprising:
a fin formed in a substrate;
wherein the fin includes an upper fin region and a lower base region;
wherein the upper fin region includes an upper fin width dimension;
wherein the lower base region includes an upper surface and a base width dimension;
wherein the base width dimension is greater than the upper fin width dimension;
wherein the lower base region further comprises a source or a drain region;
wherein the source or the drain region is configured to extend beyond the lower base region into a portion of the substrate;
wherein the source or the drain region is communicatively coupled to the upper fin region;
a trench formed in the source or the drain region;
wherein at least a portion of the trench comprises a substantially planar upper surface of the lower base region;
wherein the substantially planer upper surface of the lower base region is formed at an angle with respect to a major surface of the substrate;
a dielectric region formed in the trench;
a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region comprises at least a portion of the dielectric region; and
a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further comprises at least a portion of the bottom spacer.
6. The device of claim 5 , wherein the angle comprises greater than zero degrees and less than ninety degrees.
7. The device of claim 5 , wherein the dielectric region comprises a low-k material and the bottom spacer comprises a high-k material.
8. The device of claim 5 , wherein at least a portion of the source or the drain region is formed from the lower base region.