Semiconductor package

1. A semiconductor package comprising:

a base substrate;

a first semiconductor chip including a first through-silicon via (TSV), wherein the first TSV is stacked on the base substrate;

a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a second TSV; and

a non-conductive film formed between the first semiconductor chip and the second semiconductor chip, the non-conductive film including two layers having different viscosities,

wherein a viscosity of each of the two layers included in the non-conductive film increases in a direction away from the base substrate.

2. The semiconductor package of claim 1 ,

wherein the non-conductive film comprises a first layer and a second layer on the first layer,

wherein a lowest viscosity of the first layer is lower than a lowest viscosity of the second layer.

3. The semiconductor package of claim 2 ,

wherein the first layer comprises first ceramic fillers,

the second layer comprises second ceramic fillers, and

an average diameter of the first ceramic fillers is greater than an average diameter of the second ceramic fillers.

4. The semiconductor package of claim 2 ,

wherein a thickness of the first layer is less than a thickness of the second layer.

5. The semiconductor package of claim 2 ,

wherein the first layer contacts a top surface of the first semiconductor chip, and

the second layer contacts a bottom surface of the second semiconductor chip.

6. The semiconductor package of claim 2 ,

wherein a portion of a side surface of the second layer is covered by the first layer.

7. The semiconductor package of claim 1 , further comprising a molding member covering a side surface of the first semiconductor chip, a side surface of the second semiconductor chip, and a side surface of the non-conductive film, the molding member covering the non-conductive film.

8. The semiconductor package of claim 7 ,

wherein, when the semiconductor package is viewed in a horizontal direction, a width of the non-conductive film protruding from edges of the first semiconductor chip and the second semiconductor chip is less than a width of the molding member.

9. The semiconductor package of claim 1 ,

wherein the non-conductive film comprises flux.

10. The semiconductor package of claim 1 , further comprising connection members provided between a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip to electrically connect the first TSV with the second TSV,

wherein the non-conductive film fills a space between the connection members.

11. A semiconductor package comprising:

a base substrate;

at least two semiconductor chips stacked on the base substrate in a direction perpendicular to a top surface of the base substrate, each semiconductor chip including a through-silicon via (TSV); and

a non-conductive film between the semiconductor chips, the non-conductive film comprising at least two layers having different viscosities,

wherein a viscosity of each of the layers included in the non-conductive film increases in a direction away from the base substrate.

12. The semiconductor package of claim 11 ,

wherein the non-conductive film comprises ceramic fillers having different sizes,

wherein, in each of the layers included in the non-conductive film, an average diameter of the ceramic fillers is reduced in a direction away from the base substrate.

13. The semiconductor package of claim 11 ,

wherein the base substrate comprises any one of a printed circuit board (PCB), an interposer, a wafer, and a semiconductor chip that is a different type from the at least two semiconductor chips.

14. The semiconductor package of claim 11 , further comprising:

a first molding member covering side surfaces of the semiconductor chips and a side surface of the non-conductive film; and

a second molding member covering at least a portion of the first molding member, the second molding member disposed between the base substrate and a lowermost semiconductor chip of the at least two semiconductor chips.

15. A semiconductor package comprising:

a base substrate;

a first semiconductor chip, wherein the first semiconductor chip is stacked on the base substrate;

a second semiconductor chip stacked on the first semiconductor chip; and

a non-conductive film formed between the first semiconductor chip and the second semiconductor chip,

wherein the non-conductive film includes at least two portions, which are vertically stacked and have different viscosities, and

wherein a viscosity of each of the at least two portions included in the non-conductive film increases in a direction away from the base substrate.

16. The semiconductor package of claim 15 ,

wherein the first semiconductor chip includes a first through-silicon via (TSV) and the second semiconductor chip includes a second TSV.