IP Library › Granted Patent US 10,050,113
Granted Patent B2
US 10,050,113 · App. 15/439,986 · Granted Aug 14, 2018

Semiconductor device with needle-shaped field plates and a gate structure with edge and node portions

Inventors: Ralf Siemieniec (Villach, AT); Oliver Blank (Villach, AT); David Laforet (Villach, AT); Cedric Ouvrard (Villach, AT); Li Juin Yip (Villach, AT)
Assignee: Infineon Technologies Austria AG
H01L29/407H01L29/0696H01L29/404H01L29/4236H01L29/4238H01L29/7813H01L29/7391H01L29/7397H01L29/7827
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Quick Facts
Patent No.
US 10,050,113
App. No.
15/439,986
Granted
Aug 14, 2018
Kind
B2
Abstract

A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.

Claims (35)

1. A semiconductor device, comprising:

needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area; and

a grid structure separating the transistor sections from each other, the grid structure comprising:

stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively;

gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and

one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.

2. The semiconductor device of claim 1 , wherein the gate node portions comprise first node portions connecting two of the gate edge portions respectively.

3. The semiconductor device of claim 1 , wherein the gate node portions comprise at least one of second node portions and third node portions, the second node portions connecting three of the gate edge portions, respectively and the third node portions connecting four or more of the gate edge portions, respectively.

4. The semiconductor device of claim 2 , wherein the gate node portions are formed such that outer corners of the transistor sections have an angle of at least 120 degree.

5. The semiconductor device of claim 1 , wherein at least one of the one or more connection sections separates a gate edge portion from a gate node portion.

6. The semiconductor device of claim 1 , wherein at least one of the one or more connection sections separates two or more neighboring gate edge portions.

7. The semiconductor device of claim 1 , wherein the gate node portions are at first nodes of the grid structure and the one or more connection sections are at complementing second nodes of the grid structure.

8. The semiconductor device of claim 1 , wherein the gate node portions are formed such that a minimum distance between orthogonal gate edge portions adjoining to the gate node portions is at least 50 nm.

9. The semiconductor device of claim 1 , wherein a horizontal cross-sectional area of the gate node portions includes stripe-shaped partial areas with a width of the gate edge portions and at least one isosceles triangular partial area fitting between two of the stripe-shaped partial areas.

10. The semiconductor device of claim 9 , wherein a minimum length of the isosceles sides of the triangular partial areas is at least 50 nm.

11. The semiconductor device of claim 1 , wherein the grid structure comprises a plurality of line portions, each line portion comprising a plurality of the gate edge portions arranged along a straight line and connected through node portions, respectively.

12. The semiconductor device of claim 11 , wherein in a central portion of the transistor cell area the line portions are connected to each other through gate edge portions and gate node portions.

13. The semiconductor device of claim 12 , further comprising:

second line portions running, in the central portion, orthogonal to the first line portions and connecting the first line portions.

14. The semiconductor device of claim 11 , further comprising:

further second line portions running, in a transition region, orthogonal to the first line portions and connecting the first line portions.

15. The semiconductor device of claim 11 , further comprising:

a gate connector in a termination area, wherein the termination area surrounds the transistor cell area and is devoid of transistor cells and wherein the gate connector electrically connects gate electrodes in the line portions.

16. The semiconductor device of claim 1 , wherein the transistor sections are rectangular with beveled and/or rounded corners.

17. The semiconductor device of claim 1 , wherein the gate edge portions, the gate node portions and the one or more connection sections complement each other to a complete grid.

18. The semiconductor device of claim 1 , wherein the one or more connection sections connect two or more neighboring transistor sections, respectively.

19. The semiconductor device of claim 1 , wherein the gate edge portions are stripes of uniform width.

20. The semiconductor device of claim 1 , wherein the one or more connection sections separate at least three gate edge portions or one gate node portion and one gate edge portion from each other.

21. An electronic assembly, comprising:

a semiconductor device comprising:

needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area; and

a grid structure separating the transistor sections from each other, the grid structure comprising:

stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively;

gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and

one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: OUVRARD, CEDRIC; LAFORET, DAVID; YIP, LI JUIN; BLANK, OLIVER; SIEMIENIEC, RALF
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 042138/0890 →
Priority Claims (1)
DE 10 2016 103 581 · Feb 29, 2016 · national
Continuity (1)
Related Publication 20170250256A1 · Aug 31, 2017
Cited By (1)
US 12,713,671