Approach to minimization of strain loss in strained fin field effect transistors
View Patent ↗A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
1. A vertical fin device, comprising:
a plurality of strained, straight, vertical fin segments on a substrate, wherein each of the plurality of strained, straight, vertical fin segments has a tensile or compressive strain;
a plurality of gate spacers on each of the plurality of strained, straight, vertical fin segments;
a gate structure within each of the gate spacers;
a plurality of source/drain contacts on one or more of the plurality of strained, straight, vertical fin segments, wherein each of the plurality of source/drain contacts is adjacent to at least one of the plurality of gate spacers;
an insulating liner in contact with an endwall of two or more of the plurality of strained, straight, vertical fin segments, wherein the insulating liner extends from within the substrate to the top of the adjacent gate spacer; and
an interlevel dielectric on each of the plurality of gate spacers, the two insulating liners, and the source/drain contacts.
2. The vertical fin device of claim 1 , wherein each of the plurality of gate spacers and gate structures spans two vertical fin segments.
3. The vertical fin device of claim 1 , wherein the gate structure includes a gate dielectric, a work function layer, and a conductive gate fill layer.
4. The vertical fin device of claim 1 , wherein the insulating liner is on at least a portion of one of the plurality of gate spacers and on the substrate, and a trench fill is on the insulating liner.
5. The vertical fin device of claim 4 , wherein each of the plurality of gate spacers each has a thickness in the range of about 3 nm to about 15 nm, and the insulating liner has a thickness in the range of about 3 nm to about 15 nm.
6. The vertical fin device of claim 4 , wherein each of the plurality of gate spacers surrounds each of the gate structures on four sides.
7. The vertical fin device of claim 4 , wherein each of the plurality of strained, straight, vertical fin segments has a tensile or compressive strain in the range from 0.3% to 1.5%.
8. The vertical fin device of claim 4 , wherein each of the plurality of gate spacers is silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), a boron nitride (BN), or combinations thereof.
9. The vertical fin device of claim 8 , wherein the insulating liner is silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), boron carbide (BC), boron nitride (BN), or combinations thereof.
10. The vertical fin device of claim 8 , wherein the insulating liner has a thickness in the range of about 2 nm to about 15 nm.
11. A vertical fin device, comprising:
a plurality of strained, straight, vertical fin segments on a substrate, wherein each of the plurality of strained, straight, vertical fin segments has a tensile or compressive strain in the range from 0.3% to 1.5%;
three or more gate spacers on each of the plurality of strained, straight, vertical fin segments;
a gate structure within each of the three or more gate spacers, wherein each gate spacer and gate structure spans two vertical fin segments;
two insulating liners in contact with two or more of the plurality of strained, straight, vertical fin segments, wherein a first of the two insulating liners is in contact with an endwall of the two or more of the plurality of strained, straight, vertical fin segments, and a second of the two insulating liners is in contact with another endwall of the two or more of the plurality of strained, straight, vertical fin segments, wherein two of the plurality of strained, straight, vertical fin segments are between the second insulating liner and the first insulating liner;
a trench fill within the first insulating liner and second insulating liner; and
a source/drain contact on one or more of the plurality of strained, straight, vertical fin segments adjacent to at least one of the three or more gate spacers.
12. The vertical fin device of claim 11 , wherein the plurality of strained, straight, vertical fin segments are strained silicon-germanium (SiGe), and there are three or more gate structures on each of the strained, straight, SiGe vertical fin segments.
13. The vertical fin device of claim 11 , wherein the plurality of strained, straight, vertical fin segments are strained silicon (Si), and the substrate is single crystal silicon-germanium.
14. The vertical fin device of claim 11 , wherein the plurality of strained, straight, vertical fin segments are strained silicon-germanium (SiGe), and the substrate is single crystal silicon.
15. The vertical fin device of claim 14 , wherein the height of the vertical fin segments and the germanium (Ge) concentration of the SiGe vertical fin segments are below the threshold value at which dislocations would appear in the strained, straight, SiGe vertical fin segments.
16. A vertical fin device, comprising:
a plurality of strained, straight, vertical fin segments on a substrate, wherein each of the plurality of strained, straight, vertical fin segments has a tensile or compressive strain in the range from 0.3% to 1.5%;
a plurality of gate spacers on each of the plurality of strained, straight, vertical fin segments, wherein each of the plurality of gate spacers has a thickness in the range of about 3 nm to about 15 nm;
a gate structure within each of the plurality of gate spacers;
a source/drain contact on one or more of the plurality of strained, straight, vertical fin segments adjacent to at least one of the plurality of gate spacers;
an insulating liner in contact with an endwall of two or more of the plurality of strained, straight, vertical fin segments, wherein the insulating liner extends from within the substrate to the top of the adjacent gate spacer; and
an interlevel dielectric on each gate spacer and the source/drain contacts.
17. The vertical fin device of claim 16 , wherein each of the plurality of gate spacers surrounds each of the gate structures on four sides.
18. The vertical fin device of claim 16 , wherein the insulating liner is on at least a portion of one of the plurality gate spacers, and a trench fill is on the insulating liner, wherein the trench fill is separated from the gate structure by the thickness of the insulating liner and the thickness of one of the plurality gate spacers.
19. The vertical fin device of claim 18 , wherein the insulating liner has a thickness in the range of about 2 nm to about 15 nm.
20. The vertical fin device of claim 18 , further comprising a gate insulator cap on at least a portion of each gate structure.