IP Library › Granted Patent US 10,402,173
Granted Patent B2
US 10,402,173 · App. 15/441,626 · Granted Sep 3, 2019

Systems and methods for arbitrary software logic modeling

Inventors: Liling Ren (Niskayuna, NY); Han Yu (Niskayuna, NY); Gregory Reed Sykes (Grand Rapids, MI); Michael Richard Durling (Gansevoort, NY); Kit Yan Siu (Niskayuna, NY); Scott Alan Stacey (Dayton, OH)
Assignee: General Electric Company
G06F8/20G06F8/313G06F8/34G06F8/35G06F9/44G06F9/455G06F8/30
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Quick Facts
Patent No.
US 10,402,173
App. No.
15/441,626
Granted
Sep 3, 2019
Kind
B2
Abstract

According to some embodiments, an Arbitrary Software Logic Modeling (“ASLM”) data source may store electronic records associated with units, each electronic record including a unit identifier, one or more identification tags, context data, unit parameters, unit variables, and internal logic. An ASLM platform may express system requirements at a logic block level and establish the logic blocks as self-contained entities and connections in accordance with the system requirements (the established logic blocks graphically representing systems logic). The ASLM platform may then explicitly transform the systems logic automatically to output language agnostic common design information exchange model information. The ASLM platform may also translate and maintain traceability among the system requirements, common design information exchange model information, and generated code.

Claims (87)

1. A system to facilitate Arbitrary Software Logic Modeling (“ASLM”) processing, comprising:

an ASLM data source storing electronic records associated with units, each electronic record including a unit identifier, one or more identification tags, context data, unit parameters, unit variables, and internal logic; and

an ASLM platform, coupled to the ASLM data source, including a computer programmed to:

(i) express system requirements at a logic block level;

(ii) establish the logic blocks as self-contained entities and connections in accordance with the system requirements, the established logic blocks graphically representing systems logic;

(iii) explicitly transform the systems logic automatically to output language agnostic common design information exchange model information;

(iv) translate and maintain traceability among the system requirements, common design information exchange model information, and generated code, and

(v) execute a splitting process, including:

abstracting a nested block entity for splitting into a new unit,

creating the new unit and registering a unit identifier in a data dictionary,

establishing unit parameters for the new unit,

establishing unit variables for the new unit,

transferring nested sub-logic of the nested block entity to the new unit,

generalizing block entities and control nodes encapsulated in the new unit,

establishing identification tags for the new unit and registering the new unit in a traceability map that includes a hierarchy,

updating the nested block entity with reference to the new unit, and

updating identification tags for the nested block entity and updating the nested block entity in the traceability map and repeating updates of the identification tags and traceability map for an original unit.

2. The system of claim 1 , wherein system requirements comprise at least one of low-level requirements and high-level requirements and the unit parameters define an external unit interface and trace to an ontology to allow for automatic transformation of a software component interface, wherein the low-level requirements are below the high-level requirements in a hierarchy.

3. The system of claim 1 , wherein at least one electronic record in the ASLM data source represents a block entity, including a block identifier, one or more identification tags, arguments, block parameters, block variables, and actions.

4. The system of claim 1 , wherein the systems logic includes at least one of: control nodes, looping nodes, merge nodes, entry nodes, exit nodes, and null nodes.

5. The system of claim 1 , wherein the ASLM platform is further to execute an expansion process.

6. The system of claim 5 , wherein the expansion process includes:

elevating parent block variables of a parent block entity to unit variables;

re-mapping arguments for block entities and control nodes in nested sub-logic;

merging entry and exit nodes of nested sub-logic with control nodes in unit internal logic;

un-registering parent block identification tags from a traceability map that includes a hierarchy;

un-registering a parent block identifier from a data dictionary; and

releasing the parent block entity.

7. The system of claim 1 , wherein the ASLM platform is further to execute an abstraction process.

8. The system of claim 7 , wherein the abstraction process includes:

identifying a sub-section of logic to be abstracted;

creating a new block entity and registering a block identifier in a data dictionary;

nesting the sub-section of logic as actions of the new block entity;

connecting the new block entity to a location where the sub-section of logic originally connected;

establishing arguments for the new block entity with the nested sub-section of logic;

establishing block parameters for the nested block entity;

establishing block variables for the nested block entity; and

establishing identification tags for the nested block entity and registering the nested block entity in a traceability map that includes a hierarchy.

9. The system of claim 1 , wherein the ASLM platform is further to execute a merging process.

10. The system of claim 9 , wherein the merging process includes:

identifying a block entity in a combined unit that references a unit to be merged;

expanding block variables of a parent block entity to include unit variables from the unit to be merged;

transferring internal logic of the unit to be merged to nested sub-logic of the parent block entity;

re-mapping arguments for block entities and control nodes merged into the nested sub-logic;

updating identification tags of the parent block entity after transfer of internal logic of the unit to be merged and expansion of block variables and updating the registration of a parent block identifier in a traceability map that includes a hierarchy and updating the identification tags and traceability map for the combined unit;

un-registering identification tags of the unit to be merged from the traceability map;

un-registering a unit identifier of the unit to be merged from a data dictionary; and

releasing the unit to be merged.

11. A computerized method to facilitate Arbitrary Software Logic Modeling (“ASLM”) processing, comprising:

accessing an ASLM data source storing electronic records associated with units, each electronic record including a unit identifier, one or more identification tags, context data, unit parameters, unit variables, and internal logic;

expressing, via a computer processor of an ASLM platform, system requirements at a logic block level;

establishing the logic blocks as self-contained entities and connections in accordance with the system requirements, the established logic blocks graphically representing systems logic;

explicitly transforming the systems logic automatically to output language agnostic common design information exchange model information;

translating and maintaining traceability among the system requirements, common design information exchange model information, and generated code, and

executing a merging process, including:

identifying a block entity in a combined unit that references a unit to be merged;

expanding block variables of a parent block entity to include unit variables from the unit to be merged;

transferring internal logic of the unit to be merged to nested sub-logic of the parent block entity;

re-mapping arguments for block entities and control nodes merged into the nested sub-logic;

updating identification tags of the parent block entity after transfer of internal logic of the unit to be merged and expansion of block variables and updating the registration of the parent block identifier in a traceability map that includes a hierarchy and updating the identification tags and traceability map for the combined unit;

un-registering identification tags of the unit to be merged from the traceability map;

un-registering a unit identifier of the unit to be merged from a data dictionary; and

releasing the unit to be merged.

12. The method of claim 11 , wherein system requirements comprise at least one of low-level requirements and high-level requirements, wherein the low-level requirements are below the high-level requirements in a hierarchy.

13. The method of claim 11 , wherein at least one electronic record in the ASLM data source represents a block entity, including a block identifier, one or more identification tags, arguments, block parameters, block variables, and actions.

14. The method of claim 11 , wherein the systems logic includes at least one of: control nodes, looping nodes, merge nodes, entry nodes, exit nodes, and null nodes.

15. The method of claim 11 , wherein the ASLM platform is further to execute at least one of: an expansion process, an abstraction process, and a splitting process.

16. A non-transitory, computer-readable medium storing instructions that, when executed by a computer processor, cause the computer processor to perform a method to facilitate Arbitrary Software Logic Modeling (“ASLM”) processing, the method comprising:

accessing an ASLM data source storing electronic records associated with units, each electronic record including a unit identifier, one or more identification tags, context data, unit parameters, unit variables, and internal logic;

expressing, via a computer processor of an ASLM platform, system requirements at a logic block level;

establishing the logic blocks as self-contained entities and connections in accordance with the system requirements, the established logic blocks graphically representing systems logic;

explicitly transforming the systems logic automatically to output language agnostic common design information exchange model information;

translating and maintaining traceability among the system requirements, common design information exchange model information, and generated code, and

executing a splitting process, including:

abstracting a nested block entity for splitting into a new unit,

creating the new unit and registering a unit identifier in a data dictionary,

establishing unit parameters for the new unit,

establishing unit variables for the new unit,

transferring nested sub-logic of the nested block entity to the new unit,

generalizing block entities and control nodes encapsulated in the new unit,

establishing identification tags for the new unit and registering the new unit in a traceability map that includes a hierarchy,

updating the nested block entity with reference to the new unit, and

updating identification tags for the nested block entity and updating the nested block entity in the traceability map and repeating updates of the identification tags and traceability map for an original unit.

17. The medium of claim 16 , wherein the system requirements comprise at least one of low-level requirements and high-level requirements, wherein the low-level requirements are below the high-level requirements in a hierarchy.

18. The medium of claim 16 , wherein at least one electronic record in the ASLM data source represents a block entity, including a block identifier, one or more identification tags, arguments, block parameters, block variables, and actions.

19. The medium of claim 16 , wherein the systems logic includes at least one of: control nodes, looping nodes, merge nodes, entry nodes, exit nodes, and null nodes.

20. The medium of claim 16 , wherein the ASLM platform is further to execute at least one of: an expansion process, an abstraction process, and a merging process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: REN, LILING; YU, HAN; SYKES, GREGORY REED; DURLING, MICHAEL RICHARD; SIU, KIT YAN; STACEY, SCOTT ALAN
To: GENERAL ELECTRIC COMPANY
Reel/Frame 041369/0762 →
Continuity (1)
Related Publication 20180246703A1 · Aug 30, 2018