Integrated circuit system

1. An integrated circuit system comprising:

a host device; and

a memory module suitable for communicating with the host device according to a first protocol,

the memory module comprising:

at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and

a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol,

wherein information transferred between the host device and the memory module comprises a write request packet information which requests a write operation, and

the write request packet information comprises a first code corresponding to a command, a second code corresponding to an address, a third code for checking validity, a fourth code corresponding to data, a fifth code corresponding to an identifier (ID) of packet information, and a sixth code indicating a source of the packet information.

2. The integrated circuit system according to claim 1 , wherein the first protocol is an asynchronous protocol, and the second protocol is a synchronous protocol.

3. The integrated circuit system according to claim 1 , wherein the memory module further comprises an accelerator suitable for performing a calculation operation and the protocol converter is further suitable for transferring information between the host device, the accelerator and the at least one memory device.

4. The integrated circuit system according to claim 3 , wherein the host device comprises a central processing unit (CPU) and the accelerator comprises a circuit which is obtained by programming a field-programmable gate array (FPGA) chip.

5. The integrated circuit system according to claim 3 , wherein the accelerator comprises a dedicated hardware accelerator which performs a predetermined function.

6. The integrated circuit system according to claim 1 , wherein the information transferred between the host device and the memory module further comprises a read request packet information which requests a read operation, a read response packet information which includes a read operation result, and an acknowledgement packet information which indicates whether an error has occurred or not.

7. The integrated circuit system according to claim 6 ,

wherein the read request packet information comprises the first code, the second code, the third code, the fifth code, and the sixth code,

wherein the read response packet information comprises the first code, the third code, the fourth code, the fifth code, and the sixth code, and

wherein the acknowledgement packet information comprises the first code, the third code, the fifth code, and a seventh code corresponding to whether an error has occurred.

8. The integrated circuit system according to claim 1 , wherein the memory module comprises a dual in-line memory module (DIMM).

9. The integrated circuit system according to claim 3 , wherein the accelerator performs at least one calculation among a sorting calculation, a searching calculation, a logic calculation and a four arithmetic calculation.

10. The integrated circuit system according to claim 3 , wherein the accelerator performs a calculation operation by using written data, and outputs a result of performing the calculation operation as read data.

11. The integrated circuit system according to claim 3 , wherein the protocol converter comprises:

an input block suitable for receiving information from the host device;

a packet decoder suitable for decoding the received information, and outputting a decoding result to a first path when the received information corresponds to the at least one memory device or a second path when the received information corresponds to the accelerator;

a first conversion block suitable for generating and outputting command/address signals or data according to the second protocol, by using the decoding result of the first path;

a second conversion block suitable for generating information for controlling the accelerator, by using the decoding result of the second path;

a third conversion block suitable for generating information according to the first protocol, by using data according to the second protocol received from the at least one memory device;

a fourth conversion block suitable for generating information according to the first protocol, by using information received from the accelerator; and

an output block suitable for transmitting the information generated in the third and fourth conversion blocks, to the host device.

12. The integrated circuit system according to claim 11 , wherein the packet decoder inspects validity of the received information, and outputs a validity inspection result.

13. An integrated circuit system comprising:

a host device; and

a memory module including at least one memory device and an accelerator, and suitable for:

converting information according to a first protocol received from the host device, into information according to a second protocol and transferring the converted information to the memory devices; and

converting information according to the second protocol outputted from the memory devices, into information according to the first protocol and transferring the converted information to the host device,

wherein information transferred between the host device and the memory module comprises a write request packet information which requests a write operation, and

wherein the write request packet information comprises a first code corresponding to a command, a second code corresponding to an address, a third code for checking validity, a fourth code corresponding to data, a fifth code corresponding to an identifier (ID) of packet information, and a sixth code indicating a source of the packet information.

14. The integrated circuit system according to claim 13 , wherein the first protocol includes an asynchronous protocol, and the second protocol includes a synchronous protocol.

15. The integrated circuit system according to claim 13 , wherein the accelerator comprises a circuit which is obtained by programming a field-programmable gate array (FPGA) chip.

16. The integrated circuit system according to claim 13 , wherein the accelerator comprises a dedicated hardware accelerator which performs a predetermined function.

17. The integrated circuit system according to claim 13 , wherein information transferred between the host device and the memory module further comprises a read request packet information which requests a read operation, a read response packet information which includes a read operation result, and an acknowledgement packet information which indicates whether an error has occurred or not.

18. The integrated circuit system according to claim 17 ,

wherein the read request packet information comprises the first code, the second code, the third code, the fifth code, and the sixth code, and

wherein the read response packet information comprises the first code, the third code, the fourth code, the fifth code, and the sixth code.

19. The integrated circuit system according to claim 18 ,

wherein the acknowledgement packet information comprises the first code, the third code, the fifth code, and a seventh code corresponding to whether an error has occurred.