Semiconductor memory device and method of manufacturing the same

1. A semiconductor memory device, comprising:

a memory cell array in which a plurality of memory cells are connected in series to form a memory unit;

word lines connected to control gates of the plurality of memory cells;

a bit line connected to a first end of the memory unit;

a source line connected to a second end of the memory unit; and

a control unit that controls the memory cell array, wherein

in a write operation to the memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,

apply a program voltage to a word line corresponding to a selected memory cell, and

cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be higher than a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

2. The semiconductor memory device according to claim 1 , wherein

the voltage applied to the second word line when a threshold voltage to be provided to a selected memory cell is not less than a reference value has a negative value.

3. The semiconductor memory device according to claim 1 , wherein

in a write operation to the memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is less than a reference value,

apply a program voltage to a word line corresponding to a selected memory cell, and

cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be equal to a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

4. The semiconductor memory device according to claim 3 , wherein

the voltage applied to the second word line when a threshold voltage to be provided to a selected memory cell is not less than a reference value has a negative value.

5. The semiconductor memory device according to claim 1 , wherein

when there are a plurality of the second word lines, the control unit applies a higher voltage to a second word line which is closer to the selected memory cell.

6. The semiconductor memory device according to claim 1 , wherein

when a threshold voltage to be provided to a selected memory cell is not less than a reference value, the control unit is operative to perform a first voltage application operation and a second voltage application operation,

the first voltage application operation causing a voltage applied to the first word line to be higher than a voltage applied to the second word line, and

the second voltage application operation causing a voltage applied to the first word line to be equal to a voltage applied to the second word line.

7. The semiconductor memory device according to claim 3 , wherein

when a threshold voltage to be provided to a selected memory cell is not less than a reference value, the control unit is operative to perform a first voltage application operation and a second voltage application operation,

the first voltage application operation causing a voltage applied to the first word line to be higher than a voltage applied to the second word line, and

the second voltage application operation causing a voltage applied to the first word line to be equal to a voltage applied to the second word line.

8. The semiconductor memory device according to claim 7 , wherein

the voltage applied to the second word line when a threshold voltage to be provided to a selected memory cell is not less than a reference value has a negative value.

9. The semiconductor memory device according to claim 1 , wherein

the control unit is operative to sequentially select memory cells from the second end to perform a write operation.

10. The semiconductor memory device according to claim 9 , wherein

the voltage applied to the second word line when a threshold voltage to be provided to a selected memory cell is not less than a reference value has a negative value.

11. The semiconductor memory device according to claim 1 , wherein the memory unit includes:

a memory shaft;

a charge accumulation layer provided on a sidewall of the memory shaft; and

s conductive layer that surrounds a side surface of the memory shaft,

the charge accumulation layer is continuously provided over a plurality of the memory cells in one memory unit.

12. A method of controlling a semiconductor memory device, the semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are connected in series to form a memory unit; word lines connected to control gates of the plurality of memory cells; a bit line connected to a first end of the memory unit; and a source line connected to a second end of the memory unit,

wherein in a write operation to the memory cells, the method includes, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,

applying a program voltage to a word line corresponding to a selected memory cell, and

causing a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be equal to a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

13. The method of controlling a semiconductor memory device according to claim 12 , wherein

the voltage applied to the second word line when a threshold voltage to be provided to a selected memory cell is not less than a reference value has a negative value.

14. The method of controlling a semiconductor memory device according to claim 12 , wherein

when a threshold voltage to be provided to a selected memory cell is not less than a reference value, the method performs a first voltage application operation and a second voltage application operation,

the first voltage application operation causing a voltage applied to the first word line to be higher than a voltage applied to the second word line, and

the second voltage application operation causing a voltage applied to the first word line to be equal to a voltage applied to the second word line.

15. The method of controlling a semiconductor memory device according to claim 12 , wherein

in a write operation to the memory cells, when a threshold voltage to be provided to a selected memory cell is less than a reference value, the method further including:

applying a program voltage to a word line corresponding to a selected memory cell, and

causing a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be equal to a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

16. The method of controlling a semiconductor memory device according to claim 15 , wherein

when a threshold voltage to be provided to a selected memory cell is not less than a reference value, the method performs a first voltage application operation and a second voltage application operation,

the first voltage application operation causing a voltage applied to the first word line to be higher than a voltage applied to the second word line, and

the second voltage application operation causing a voltage applied to the first word line to be equal to a voltage applied to the second word line.