Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
View Patent ↗This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.
1. A digital synchronous circuit comprising:
a first flip flop operable to receive a first clock signal, wherein the first flip flop is configured such that the first flip flop is synchronized to be transparent and to be opaque in accordance with the first clock signal; and
a second flip flop operable to receive a second clock signal, wherein the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with the second clock signal and wherein the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque;
wherein the first flip flop is configured to generate a first logical output such that the first flip flop is configured to set up the first logical output while the first flip flop is transparent and to hold the first logical output while the first flip flop is opaque, and the second flip flop comprises a first differential sense amplifier configured to generate a first differential logical output in a precharge state while the second clock signal is in the first clock state and is configured to generate the first differential logical output in a variable differential logical state while the second clock signal is in the second clock state, and
wherein the second flip flop is configured to generate a second logical output such that the second flip flop is configured to set up the second logical output while the second flip flop is transparent and to hold the second logical output while the second flip flop is opaque, and the second flip flop is further configured to generate the first clock signal in the first clock state in response to the first differential logical output being in the precharge state and is configured to generate the first clock signal in the second clock state in response to the first differential logical output being in the variable differential logical state.
2. The digital synchronous circuit of claim 1 wherein the second clock signal is a global clock signal.
3. The digital synchronous circuit of claim 1 further comprising a sequential state circuit that includes the first flip flop, the second flip flop, and a local clock path connected between the first flip flop and the second flip flop so that the first flip flop is operable to receive the first clock signal from the second flip flop along the local clock path.
4. The digital synchronous circuit of claim 3 further comprising a global clock tree, wherein the second flip flop is configured to receive the second clock signal as a global clock signal from the global clock tree.
5. The digital synchronous circuit of claim 4 wherein:
the second flip flop defines a characteristic propagation delay; and
the local clock path defines a characteristic path delay;
wherein the first flip flop is configured to receive the first clock signal such that a clock skew between the first clock signal and the second clock signal is approximately equal to an aggregation of the characteristic propagation delay and the characteristic path delay.
6. The digital synchronous circuit of claim 1 wherein the second flip flop is configured to generate the first clock signal so as to provide a clock skew between the first clock signal and the second clock signal.
7. The digital synchronous circuit of claim 1 further comprising a first combinational logic cone wherein:
the first flip flop is configured to receive a first data input generated by the first combinational logic cone; and
the first flip flop is configured to be transparent so as to set up the first logical output in accordance with the first data input while the first clock signal is in the first clock state.
8. The digital synchronous circuit of claim 1 wherein the second flip flop further comprises AND logic configured to receive the first differential logical output and generate the first clock signal in the first clock state in response to the second logical output being set up and to generate the first clock signal in the second clock state in response to the second clock signal being held.
9. The digital synchronous circuit of claim 1 wherein the first differential sense amplifier defines a first characteristic propagation delay and AND logic defines a second characteristic propagation delay such that the second flip flop generates the first clock signal such that a clock skew between the first clock signal and the second clock signal is approximately equal to the first characteristic propagation delay and the second characteristic propagation delay.
10. The digital synchronous circuit of claim 8 wherein the second flip flop further comprises an SR latch configured to receive the first differential logical output and generate the second logical output so that the second logical output is set up while the second clock signal is in the first clock state and the second logical output is held while the second clock signal is in the second clock state.
11. The digital synchronous circuit of claim 1 wherein the first flip flop comprises the first differential sense amplifier configured to generate the first differential logical output in the precharge state and in the variable differential logic state.
12. The digital synchronous circuit of claim 11 wherein the first flip flop comprises an SR latch configured to receive the first differential logical output and generate the first logical output so that the first logical output is set up while the first clock signal is in the first clock state and the first logical output is held while the second clock signal is in the second clock state.
13. The digital synchronous circuit of claim 1 wherein the second flip flop is configured to receive the first logical output from the first flip flop as a first data input and the second flip flop is configured to be transparent so as to set up the second logical output in accordance with the first logical output while the second clock signal is in the first clock state.
14. The digital synchronous circuit of claim 1 wherein the first flip flop is a D flip flop.
15. The digital synchronous circuit of claim 1 wherein the digital synchronous circuit is operable in a normal mode and in a scan mode.
16. The digital synchronous circuit of claim 15 further comprising a first combinational logic cone and wherein:
the first flip flop is configured to generate the first logical output such that the first flip flop is configured to set up the first logical output while the first flip flop is transparent and hold the first logical output while the first flip flop is opaque; and
the first flip flop is configured to receive a first data input generated by the combinational logic cone in the normal mode and is configured to receive a global test input in the scan mode.
17. The digital synchronous circuit of claim 16 wherein:
the second flip flop is configured to generate the second logical output such that the second flip flop is configured to set up the second logical output while the second flip flop is transparent and is configured to hold the second logical output while the second flip flop is opaque; and
the second flip flop is configured to receive the first logical output from the first flip flop as a second data input in the normal mode and is configured to receive a third logical output from a third flip flop in the scan mode.