Display device with clock signal modification during vertical blanking period
A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.
1. A display apparatus comprising:
a display panel comprising a pixel which is connected to a gate line and a data line;
a gate driver configured to generate a gate signal that swings between a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal; and
a gate controller configured to generate a clock signal that has a plurality of first pulses having a first high level, and a low level, during an active period of a frame cycle and that has a plurality of second pulses having a second high level and the low level during a vertical blanking period of the frame cycle following the active period, and to provide the gate driver with the clock signal,
wherein the second high level is lower than the first high level.
2. The display apparatus of claim 1 , wherein a duty ratio of the second pulses is equal to a duty ratio of the first pulses.
3. The display apparatus of claim 1 , wherein the clock signal maintains the low level during at least one horizontal period in the vertical blanking period.
4. The display apparatus of claim 3 , wherein the vertical blanking period includes an early portion, a middle portion and a late portion, and the clock signal maintains the low level in the middle portion.
5. The display apparatus of claim 1 , further comprising:
a driving voltage generator configured to generate the gate-on voltage and the gate-off voltage using an input voltage, and a second pulse swings between the input voltage and a gate-off voltage, the gate-off voltage being lower than the input voltage.
6. The display apparatus of claim 1 , wherein the clock signal is a first clock signal, and the gate controller is configured to generate a second clock signal having opposite phase to the first clock signal in the active period and having a same phase as the first clock signal in the vertical blanking period, wherein during the vertical blanking period, rising edges of the first clock signal are synchronized with rising edges of the second clock signal, and falling edges of the first clock signal are synchronized with falling edges of the second clock signal.
7. A display apparatus comprising:
a display panel comprising a pixel which is connected to a gate line and a data line;
a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal; and
a gate controller configured to generate a clock signal that has a plurality of first pulses having a first high level and a low level during an active period of a frame cycle and that has a plurality of second pulses having a second high level and the low level during a vertical blanking period of the frame cycle following the active period, and to provide the gate driver with the clock signal,
wherein the second high level is lower than the first high level, and
wherein a second pulse swings between a ground voltage and a gate-off voltage, the gate-off voltage being lower than the ground voltage in the vertical blanking period.
8. A display apparatus comprising:
a display panel comprising a pixel which is connected to a gate line and a data line;
a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal; and
a gate controller configured to generate a clock signal having a high level and a low level and to provide the gate driver with the clock signal,
wherein the clock signal swings between the high level and the low level in an early portion and a late portion of the vertical blanking period, and maintains the low level in a middle portion of the vertical blanking period.
9. The display apparatus of claim 8 , wherein the clock signal has a duty ratio, and a duty ratio of the clock signal in the early and late portions of the vertical blanking period is equal to a duty ratio of the clock signal in the active period.
10. The display apparatus of claim 8 , wherein the clock signal swings between the gate-on voltage and the gate-off voltage being lower than a ground voltage in the vertical blanking period.
11. The display apparatus of claim 8 , wherein the early, middle and late portions of the vertical blanking period comprise a plurality of horizontal periods, respectively.
12. The display apparatus of claim 8 , wherein the gate controller is configured to generate a first clock signal and a second clock signal having a same phase as the first clock signal in the vertical blanking period.
13. The display apparatus of claim 8 , wherein the clock signal swings from the high level to the low level a plurality of times during the early portion of the vertical blanking period.
14. The display apparatus of claim 8 , wherein the clock signal swings from the low level to the high level at a time after initiation of the vertical blanking period, and during the early portion of the vertical blanking period.
15. A display apparatus comprising:
a display panel having a pixel connected between a gate line and a data line;
a gate driver connected to the gate line and configured to generate a gate signal having at least one gate-on voltage and at least one gate-off voltage and to provide the gate line with the gate signal; and
a gate controller connected to the gate driver and configured to generate a clock signal that has a plurality of first pulses having a first high level and a low level during an active period of a frame cycle and that has a plurality of second pulses having a second high level and the low level during a vertical blanking period of the frame cycle following the active period, and to provide the gate driver with the clock signal,
wherein an amplitude of a second pulse is smaller than an amplitude of a first pulse.
16. The display apparatus of claim 15 wherein a duty ratio of the second pulses is smaller than the duty ratio of the first pulses.
17. The display apparatus of claim 15 wherein the second high level is lower than the first high level.
18. The display apparatus of claim 15 wherein the clock signal swings between the second high level and the low level in an early portion and a late portion of the vertical blanking period, and maintains the low level in a middle portion of the vertical blanking period.
19. The display apparatus of claim 15 wherein the gate-on voltage of the gate signal is substantially the same as the first high level of the clock signal, and the gate-off voltage of the gate signal is different than the low level of the clock signal.
20. The display apparatus of claim 15 wherein the clock signal is a first clock signal, and the gate controller generates a second clock signals having opposite phase to the first clock signal in an active period, and having a same phase as the first clock signal in a vertical blanking period.