Asymmetric vertical device

1. A semiconductor structure comprising:

a semiconductor fin extending upwards from a semiconductor substrate portion and including a channel region and a bottommost fin portion, wherein the channel region has outermost sidewalls that are vertically aligned to outermost sidewalls of the bottommost fin portion;

an insulator layer portion laterally surrounding, and directly contacting, the outermost sidewalls of the bottommost fin portion of the semiconductor fin and located entirely on a topmost surface of the semiconductor substrate portion;

a source region comprising a first doped fin region located within a bottom portion of the semiconductor fin, and a first doped epitaxial semiconductor region present on outermost sidewalls of the first doped fin region and having a bottommost surface that is in direct physcially contact with a topmost surface of the insulator layer portion, wherein the first doped fin region entirely separates the bottommost fin portion from the channel region;

a drain region comprising a second doped fin region located within a top portion of the semiconductor fin and a second doped epitaxial semiconductor region present on a topmost surface and outermost sidewalls of the second doped fin region;

a metal gate structure present along the outermost sidewalls of the channel region of the semiconductor fin and between the first doped fin region and the second doped fin region, wherein the metal gate structure vertically contacts the first doped epitaxial semiconductor region; and

a drain spacer located between the metal gate structure and the second doped epitaxial semiconductor region.

2. The semiconductor structure of claim 1 , wherein the metal gate structure comprises a gate dielectric laterally contacting the outermost sidewalls of the channel region and vertically contacting the first doped epitaxial semiconductor region, and a gate electrode located on the gate dielectric, wherein the drain spacer separates the gate electrode from the second doped epitaxial semiconductor region.

3. The semiconductor structure of claim 2 , wherein a horizontal portion of the gate dielectric is in direct contact with a portion of the first doped epitaxial semiconductor region that is adjoined to the semiconductor fin.

4. The semiconductor structure of claim 2 , wherein a thickness of the gate dielectric is less than a thickness of the drain spacer.

5. The semiconductor structure of claim 1 , further comprising a source spacer located over another portion of the first doped epitaxial semiconductor region that is distal from the semiconductor fin.

6. The semiconductor structure of claim 5 , wherein the metal gate structure comprises a first portion of a first width in direct contact with the first doped epitaxial semiconductor region and a second portion of a second width overlying the first portion and in direct contact with the source spacer, wherein the second width is greater than the first width.

7. The semiconductor structure of claim 5 , wherein the source spacer comprises an oxide of a semiconductor material that provides the first doped epitaxial semiconductor region.

8. The semiconductor structure of claim 1 , wherein a dopant concentration of the first doped epitaxial semiconductor region is greater than a dopant concentration of the second doped epitaxial semiconductor region.

9. The semiconductor structure of claim 1 , further comprising a gate contact structure contacting a gate electrode in the metal gate structure, a source contact structure contacting the first doped epitaxial semiconductor region, and a drain contact structure contacting the second doped epitaxial semiconductor region.

10. The semiconductor structure of claim 1 , further comprising another semiconductor fin located in a different region of the semiconductor substrate portion, wherein the first doped epitaxial semiconductor region merges the semiconductor fin and the another semiconductor fin.