Multilayer pillar for reduced stress interconnect and method of making same
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
1. A method comprising:
forming a barrier and adhesion layer that connects a modulated copper pillar to a chip;
forming a seed layer contacting the barrier and adhesion layer;
forming a first copper layer contacting the seed layer;
forming a second copper layer contacting a solder material;
forming at least one deformation region, wherein the at least one-deformation region is between the first copper layer and the second copper layer and has a modulus of elasticity less than copper;
forming a first protective layer interposed at an interface between a surface of the at least one deformation region and the first copper layer; and
forming a second protective layer interposed at an interface between a surface of the second copper layer and the at least one deformation region and the second copper layer, wherein:
the first protective layer is a layer of nickel covering the entire surface of the at least one deformation region; and
the second protective layer is another layer of nickel covering the entire surface of the at least one deformation region.
2. The method of claim 1 , wherein the at least one deformation region comprises two separate deformation regions between the first copper layer and the second copper layer.
3. The method of claim 2 , further comprising forming a third copper layer between the two separate deformation regions.
4. The method of claim 1 , wherein the barrier and adhesion layer prevents diffusion of materials between the chip and materials of the modulated copper pillar.
5. The method of claim 1 , wherein the at least one deformation region includes one of gold, aluminum and silver.
6. The method of claim 5 , wherein the at least one deformation region is about 0.2 to 1 microns in thickness.
7. The method of claim 1 , wherein the solder material contacts a via in a substrate.
8. The method of claim 1 , wherein a vertical sidewall of the first copper layer is aligned with both a vertical sidewall of an intermediate layer and a vertical sidewall of the second copper layer.
9. A method comprising:
forming a barrier and adhesion layer that connects a modulated copper pillar to a chip;
forming a seed layer contacting the barrier layer and adhesion layer;
forming a first copper layer contacting the seed layer;
forming a second copper layer contacting a solder material;
forming at least one deformation region, wherein the at least one deformation region is between the first copper layer and the second copper layer and has a modulus of elasticity less than copper;
forming a first nickel layer between and contacting the first copper layer and the at least one deformation region; and
forming a second nickel layer between and contacting the second copper layer and the at least one deformation region.