Calibration of inverting amplifier based impedance analyzers
A circuit for measuring an impedance of a device under test (DUT). The circuit includes: (i) circuitry for generating a stimulus wave at a stimulus frequency; (ii) an amplifier circuit coupled to the DUT to present a response signal from the DUT in response to the stimulus wave; (iii) switching circuitry for selectively coupling, between the stimulus wave and an input to the amplifier, either the DUT, a first calibration impedance, or a second calibration impedance. With the switching functionality, calibrations are performed so to provide a measure of impedance of the DUT in response to the plural calibrations.
1. A circuit, comprising:
stimulus circuitry having a stimulus output, the stimulus circuitry configured to generate a stimulus wave at the stimulus output;
an amplifier circuit having an amplifier input and an amplifier output;
switching circuitry coupled between the stimulus output and the amplifier input, the switching circuitry adapted to be coupled to a device under test (DUT), the switching circuitry adapted to be coupled to a first calibration impedance device, the switching circuitry adapted to be coupled to a second calibration impedance device, and the switching circuitry configured to selectively couple, between the stimulus output and the amplifier input, either the DUT, the first calibration impedance device or the second calibration impedance device; and
processor circuitry coupled to the amplifier output, the processor circuitry configured to:
sample a first signal from the amplifier output when the switching circuitry couples the first calibration impedance device between the stimulus output and the amplifier input;
sample a second signal from the amplifier output when the switching circuitry couples the second calibration impedance device between the stimulus output and the amplifier input;
sample a third signal from the amplifier output when the switching circuitry couples the DUT between the stimulus output and the amplifier input, the third signal representing a response of the DUT to the stimulus wave; and
in response to the first, second and third signals, provide a measure of impedance of the DUT.
2. The circuit of claim 1 , further comprising an analog-to-digital converter (ADC) through which the processor circuitry is coupled to the amplifier output, the ADC having an ADC input and an ADC output, the ADC input coupled to the amplifier output, and the ADC configured to: sample analog versions of the first, second and third signals from the amplifier output; and generate digital versions of the first, second and third signals at the ADC output, which is coupled to the processor circuitry.
3. The circuit of claim 1 , wherein the processor circuitry is coupled to the switching circuitry and configured to control the switching circuitry.
4. The circuit of claim 1 , wherein the processor circuitry is configured to provide the measure of impedance of the DUT in response to a multiplier and an offset determined from the first and second signals.
5. The circuit of claim 1 , wherein the processor circuitry is configured to provide the measure of impedance of the DUT in response to a multiplier determined from the first and second signals.
6. The circuit of claim 1 , wherein the processor circuitry is configured to provide the measure of impedance of the DUT in response to an offset determined from the first and second signals.
7. The circuit of claim 1 , wherein the stimulus wave comprises a sinusoidal stimulus wave.
8. The circuit of claim 1 , wherein the stimulus wave comprises a non-sinusoidal stimulus wave.
9. The circuit of claim 1 , wherein the stimulus wave comprises a square stimulus wave.
10. The circuit of claim 9 , further comprising an anti-aliasing filter coupled between the stimulus output and the switching circuitry.
11. The circuit of claim 4 :
wherein the multiplier comprises a representation of a transconductance of the amplifier circuit and a reference impedance; and
wherein the offset comprises a model of degradation of a virtual ground of the amplifier circuit.
12. A method, comprising:
generating a stimulus wave at a stimulus output;
selectively coupling, between the stimulus output and an amplifier input of an amplifier, either a device under test (DUT), a first calibration impedance device or a second calibration impedance device;
sampling a first signal from an amplifier output of the amplifier when the first calibration impedance device is coupled between the stimulus output and the amplifier input;
sampling a second signal from the amplifier output when the second calibration impedance device is coupled between the stimulus output and the amplifier input;
sampling a third signal from the amplifier output when the DUT is coupled between the stimulus output and the amplifier input, the third signal representing a response of the DUT to the stimulus wave; and
in response to the first, second and third signals, providing a measure of impedance of the DUT.
13. The method of claim 12 , wherein providing the measure of impedance of the DUT is responsive to a multiplier and an offset determined from the first and second signals.
14. The method of claim 12 , wherein providing the measure of impedance of the DUT is responsive to a multiplier determined from the first and second signals.
15. The method of claim 12 , wherein providing the measure of impedance of the DUT is responsive to an offset determined from the first and second signals.
16. The method of claim 12 , wherein the stimulus wave comprises a sinusoidal stimulus wave.
17. The method of claim 12 , wherein the stimulus wave comprises a non-sinusoidal stimulus wave.
18. The method of claim 12 , wherein the stimulus wave comprises a square stimulus wave.