Semiconductor memory device

1. A semiconductor memory device comprising:

first and second memory cell arrays; and

first and second control circuits configured to execute an operation on the first and second memory cell arrays, wherein

the first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device, and

the second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array, and wherein

the second control circuit is in an idle state at the time the second command set is received and the second control circuit transitions from the idle state to an active state responsive to the second command set.

2. The device according to claim 1 , wherein the first command set includes a read command and an address designating the first memory cell array, and the third command set includes a read command and an address designating the second memory cell array.

3. The device according to claim 2 , wherein the first control circuit further executes an operation on the first memory cell array responsive to a fourth command set that is received by the semiconductor memory device while the second control circuit is executing the operation on the second memory cell array, the fourth command set including a cache read command to perform a read at an address that is contiguous to the address included in the first command set.

4. The device according to claim 1 , further comprising:

a first multiplexer configured to select a first control signal from the first control circuit for executing an operation on the first or second memory cell array, or a second control signal from the second control circuit for executing an operation on the first or second memory cell array, in accordance with a first selection signal; and

a second multiplexer configured to select the first control signal from the first control circuit or the second control signal from the second control circuit, in accordance with a second selection signal.

5. The device according to claim 4 , further comprising:

a voltage generation circuit configured to generate voltages for executing the operation on the first or second memory cell array in response to the first or second control signal received from the first and second multiplexers.

6. The device according to claim 5 , wherein the voltage generation circuit includes a first booster configured to generate voltages for executing the operation on the first memory cell array and a second booster configured to generate voltages for executing the operation on the second memory cell array.

7. The device according to claim 1 , further comprising:

a third memory cell array;

a first multiplexer configured to select a first control signal from the first control circuit for executing an operation on the first, second, or third memory cell array, or a second control signal from the second control circuit for executing an operation on the first, second, or third memory cell array, in accordance with a first selection signal;

a second multiplexer configured to select the first control signal from the first control circuit or the second control signal from the second control circuit, in accordance with a second selection signal; and

a third multiplexer configured to select the first control signal from the first control circuit or the second control signal from the second control circuit, in accordance with a third selection signal.

8. The device according to claim 1 , further comprising:

a third memory cell array;

a third control circuit configured to execute an operation on the third memory cell arrays;

a first multiplexer configured to select a first control signal from the first control circuit for executing an operation on the first, second, or third memory cell array, a second control signal from the second control circuit for executing an operation on the first, second, or third memory cell array, or a third control signal from the third control circuit for executing an operation on the first, second, or third memory cell array, in accordance with a first selection signal;

a second multiplexer configured to select the first control signal from the first control circuit, the second control signal from the second control circuit, or the third control signal from the third control circuit, in accordance with a second selection signal; and

a third multiplexer configured to select the first control signal from the first control circuit, the second control signal from the second control circuit, or the third control signal from the third control circuit, in accordance with a third selection signal.

9. The device according to claim 1 , further comprising:

a ready/busy control circuit configured to output a busy signal when both the first and second control circuits are in an active state and to output a ready signal when at least one of the first and second control circuits is not in the active state.

10. The device according to claim 9 , further comprising:

an input/output circuit configured to output a plurality of output input/output signals including a first input/output signal indicating whether or not the first control circuit is in the active state and a second input/output signal indicating whether or not the second control circuit is in the active state.

11. The device according to claim 1 , wherein the operation executed on the first memory cell array is one of a read operation, a write operation, and an erase operation.

12. The device according to claim 11 , wherein the operation executed on the second memory cell array is a read operation.

13. The device according to claim 11 , wherein the operation executed on the second memory cell array is a refresh operation.

14. A method of performing a multi-plane operation in a semiconductor memory device including first and second memory cell arrays, said method comprising:

receiving a first command set;

executing an operation on the first memory cell array in accordance with the first command set; and

receiving a second command set and executing an operation on the second memory cell array in accordance with the second command set, while the operation on the first memory cell array is being executed, wherein

the first command set includes a read command and an address designating the first memory cell array, and the second command set includes a read command and an address designating the second memory cell array.

15. The method according to claim 14 , further comprising:

receiving a third command set while the operation on the second memory cell array is being executed, wherein

the third command set includes a cache read command to perform a read at an address that is contiguous to the address included in the first command set.

16. The method according to claim 14 , wherein the semiconductor memory device further includes a third memory cell array, said method further comprising:

receiving a third command set and executing an operation on the third memory cell array in accordance with the third command set, while the operation on the first memory cell array and the operation on the second memory cell array are being executed.

17. The method according to claim 14 , further comprising:

outputting a busy signal when the operation on the first memory cell array and the operation on the second memory cell array are both being executed; and

outputting a ready signal when either the operation on the first memory cell array or the operation on the second memory cell array, is not being executed.

18. The method according to claim 17 , further comprising:

outputting a status of the operation on the first memory cell array through a first input/output signal and a status of the operation on the second memory cell array through a second input/output signal.