Storage device for transmitting data having an embedded command in both directions of a shared channel, and a method of operating the storage device
A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
1. A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method comprising:
transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and
transmitting a command to the second memory device through the data signal line, wherein the first data and the command are loaded on the data signal line at the same time,
wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and
the first data and the command are transmitted in both directions of the data signal line.
2. The method of claim 1 , wherein the first data is transmitted to the memory controller at a transmission rate of a first frequency, and the command is transmitted to the second memory device at a transmission rate of a second frequency,
wherein the first frequency is higher than the second frequency.
3. The method of claim 1 , wherein a state of the data signal line is changed to a state of a high voltage level when a command signal bit for the second memory device is logic high, and is changed to a state of a low voltage level when the command signal bit is logic low,
wherein the high voltage level is higher than a second reference voltage level that is between a power voltage level and a ground voltage level of the storage device, and the low voltage level is lower than the second reference voltage level.
4. The method of claim 3 , further comprising:
extracting, by the memory controller, internal data corresponding to the first data received through the data signal line,
wherein the extracting of the internal data includes:
comparing, by the memory controller, the first data, loaded in the state of the low voltage level on the data signal line, with a first reference voltage level that is lower than the second reference voltage level and outputting the internal data; and
comparing, by the memory controller, the first data, loaded in the state of the high voltage level on the data signal line, with a third reference voltage level that is higher than the second reference voltage level and outputting the internal data.
5. The method of claim 3 , further comprising:
extracting, by the second memory device, an internal command corresponding to the command for the second memory device received through the data signal line,
wherein the extracting of the internal command includes comparing, by the second memory device, the command for the second memory device, loaded on the data signal line, with the second reference voltage level and outputting the internal command.
6. The method of claim 1 , further comprising:
transmitting, by the memory controller, a first page read command to the first memory device;
performing, by the first memory device, a first page read operation for memory cells in response to the first page read command; and
transmitting, by the memory controller, a first random read command to the first memory device after the first page read operation is performed,
wherein the first memory device transmits the first data to the memory controller in response to the first random read command, and
the command for the second memory device is a second random read command applied to the second memory device.
7. The method of claim 6 , further comprising:
transmitting, by the memory controller, a second page read command to the second memory device after transmitting the first page read command to the first memory device; and
performing, by the second memory device, a second page read operation for memory cells in response to the second page read command,
wherein the second random read command is transmitted to the second memory device when the first data of the first memory device is output through the data signal line after the second page read operation is performed.
8. A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method comprising:
transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and
transmitting write data for the second memory device to the second memory device through the data signal line, wherein the first data and the write data are loaded on the data signal line at the same time,
wherein a voltage level of the data signal line is based on the write data and the first data is loaded on the data signal, and
the first data and the write data are transmitted in both directions of the data signal line in the single channel.
9. The method of claim 8 , wherein the first data is transmitted to the memory controller at a transmission rate of a first frequency, and the write data is transmitted to the second memory device at a transmission rate of a second frequency,
wherein the first frequency is higher than the second frequency.
10. The method of claim 8 , wherein a state of the data signal line is changed to a state of a high voltage level when a write data bit for the second memory device is logic high, and is changed to a state of a low voltage level when the write data bit is logic low,
wherein the high voltage level is higher than a second reference voltage level that is between a power voltage level and a ground voltage level of the storage device, and the low voltage level is lower than the second reference voltage level.
11. The method of claim 10 , further comprising:
extracting, by the memory controller, internal data corresponding to the first data received through the data signal line,
wherein the extracting of the internal data includes:
comparing, by the memory controller, the first data, loaded in the state of the low voltage level on the data signal line, with a first reference voltage level that is lower than the second reference voltage level and outputting the internal data; and
comparing, by the memory controller, the first data, loaded in the state of the high voltage level on the data signal line, with a third reference voltage level that is higher than the second reference voltage level and outputting the internal data.
12. The method of claim 10 , further comprising:
extracting, by the second memory device, internal write data corresponding to the write data received through the data signal line,
wherein the extracting of the internal write data includes
comparing, by the second memory device, the write data, loaded on the data signal line, with the second reference voltage level and outputting the internal write data.