IP Library Granted Patent US 9,986,185
Granted Patent B2
US 9,986,185 · App. 15/447,281 · Granted May 29, 2018

Semiconductor integrated circuit and image capturing apparatus

Inventors: Sho Kamezawa (Osaka, JP); Tohru Kanno (Kanagawa, JP); Yuuya Miyoshi (Osaka, JP)
Assignee: RICOH COMPANY, LTD.
H04N5/3698H03K17/687H04N5/378
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,986,185
App. No.
15/447,281
Granted
May 29, 2018
Kind
B2
Abstract

A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.

Claims (25)

1. A semiconductor integrated circuit, comprising:

multiple signal processing circuits arranged in row along one direction, each signal processing circuit including a constant current source;

a first bias source disposed at one end of the row of the multiple signal processing circuits and to generate first bias voltage in accordance with supplied current;

a second bias source disposed at another end of the row of the multiple signal processing circuits and to generate second bias voltage in accordance with supplied current;

a first bias circuit to supply a first reference current to the first bias source;

a second bias circuit to supply a second reference current to the second bias source;

a bias wiring to supply the first bias voltage generated by the first bias voltage and the second bias voltage generated by the second bias voltage, respectively, to a plurality of gates of a transistor that constructs the constant current source;

a power source wiring to supply a power source voltage to each of the first bias source, the second bias source, and the constant current source;

a first voltage supplying source disposed at the one end of the row of the multiple signal processing circuits and to apply a first power source voltage to the power source wiring; and

a second voltage supplying source disposed at the other end of the row of the multiple signal processing circuits and to apply a second power source voltage to the power source wiring.

2. The semiconductor integrated circuit according to claim 1 ,

wherein the power source wiring is separated from another wiring that supplies power source voltage to another circuit.

3. The semiconductor integrated circuit according to claim 1 ,

wherein the signal processing circuit performs at least any one of analog signal processing operation, correlated double sampling processing operation, analog/digital conversion processing operation, and digital signal processing operation.

4. The semiconductor integrated circuit according to claim 1 ,

wherein the constant current source supplies current to a load circuit via a current mirror circuit including two transistors whose size ratio is configured so that an input current becomes larger than an output current.

5. The semiconductor integrated circuit according to claim 1 , further comprising:

a first switch to turn on and off a first connection between the first bias source and the bias wiring; and

a second switch to turn on and off a second connection between the second bias source and the bias wiring,

wherein both the first switch and the second switch are simultaneously turned on during a sampling period and simultaneously turned off during a holding period.

6. An image capturing apparatus, comprising,

the semiconductor integrated circuit according to claim 1 to perform photoelectric conversion;

an optical system to form an image on the semiconductor integrated circuit;

an image processor to perform various signal processing operations on an image signal output by the semiconductor integrated circuit; and

a controller to control the semiconductor integrated circuit and the image processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2017
From: KAMEZAWA, SHO; KANNO, TOHRU; MIYOSHI, YUUYA
To: RICOH COMPANY, LTD.
Reel/Frame 041437/0344 →
Priority Claims (2)
JP 2016-045109 · Mar 9, 2016 · national
JP 2016-255001 · Dec 28, 2016 · national
Continuity (1)
Related Publication 20170264844A1 · Sep 14, 2017