Method of fabricating an integrated circuit with non-printable dummy features

1. An integrated circuit (IC) fabrication method comprising:

extracting, by a computer processor, an IC design layout presented in one or more data files, the IC design layout designed to be formed on a semiconductor substrate and a plurality of main features and a plurality of space blocks;

calculating, by the computer processor, an optimized block dummy density ratio r 0 of the IC design layout to obtain an optimized uniformity of pattern density (UPD), the optimized block dummy density ratio r 0 being calculated from a total pattern density associated with a subdivisional area of the IC design layout;

determining a target block dummy density ratio R of the IC design layout according to the optimized block dummy density ratio r 0 ;

choosing a type of dummy features according to an associated maximum intensity that is less than an exposure threshold dose of at least one of the main features;

generating a pattern of the dummy features according to the target block dummy density ratio R;

generating a modified IC design layout by adding the dummy features to the IC design layout; and

fabricating an integrated circuit according to the modified IC design layout.

2. The method of claim 1 , wherein the generating the pattern of the dummy features comprises determining a size and pitch of the dummy features to have the associated maximum intensity be less than the exposure threshold dose of the main features.

3. The method of claim 1 , wherein the dummy features are not printable in a lithography process.

4. The method of claim 1 , wherein the generating the pattern of the dummy features includes generating square type features with size A and configured in an array with a pitch p such that a ratio A 2 /p 2 is equal to the target block dummy density ratio R.

5. The method of claim 1 , wherein the generating the pattern of the dummy features includes generating rectangle type features that spans a first dimension A in a first direction and a second dimension B in a second direction orthogonal to the first direction, wherein the dummy features are configure in an array with a first pitch p x in the first direction and a second pitch p y in the second direction such that a ratio AB/(p x p y ) is equal to the target block dummy density ratio R.

6. The method of claim 1 , wherein the generating the pattern of the dummy features includes generating rectangle type features that spans a first dimension A in a first direction and a second dimension B in a second direction that is not orthogonal to the first direction, wherein the dummy features are configure in an array with a first pitch p x in the first direction and a second pitch p y in the second direction such that a ratio AB/(p x p y ) is equal to the target block dummy density ratio R.

7. The method of claim 1 , wherein the generating of the dummy features includes generating an irregular dummy array, such that a total dummy area/space block area is equal to the target block dummy density ratio R.

8. The method of claim 1 , wherein the dummy features include an optical proximity correction feature that enhances imaging resolution.

9. The method of claim 1 , wherein the IC design layout includes a plurality of subdivisional areas, wherein the subdivisional area is one of the plurality of subdivisional areas, and wherein at least one of the plurality of subdivisional areas includes a plurality of main features and a plurality of space blocks.

10. The method of claim 1 , wherein the optimized block dummy density ratio r 0 is calculated by a formula r 0 =( PD 0 · PD S − PD 0 · PD S )/σ s 2 wherein:

PD 0 is an average of a main pattern density;

PD S is an average of a block dummy pattern density;

PD 0 · PD S is an average of a product of the main pattern density and the block dummy pattern density; and

σ is defined by a formula σ 2 = PD 2 − PD 2 , where PD is a total pattern density defined in a formula PD=PD 0 +rPD S and r is a block dummy density ratio, σ S is defined by a formula σ S 2 = PD S 2 − PD S 2 .

11. The method of claim 1 , wherein the determining the target block dummy density ratio R of the IC design layout is further according to process window and throughput.

12. The method of claim 1 , wherein the associated maximum intensity is lower than a model threshold by a predetermined margin, wherein the model threshold is based on a simulated critical dimension.

13. The method of claim 1 , wherein the generating the modified IC design layout by adding the dummy features to the IC design layout comprises adding the dummy features to a polysilicon design layer included in the modified IC design layout.

14. An integrated circuit (IC) fabrication method comprising:

extracting, by a computer processor, an IC design layout presented in one or more data files, the IC design layout designed to be formed on a semiconductor substrate and including a subdivisional area, wherein the subdivisional area includes a plurality of main features and a plurality of space blocks;

calculating, by the computer processor, an optimized block dummy density ratio r 0 of the IC design layout to obtain an optimized uniformity of pattern density (UPD), the optimized block dummy density ratio r 0 being calculated from a total pattern density associated with the subdivisional area of the IC design layout;

determining a target block dummy density ratio R of the IC design layout according to the optimized block dummy density ratio r 0 and processing window;

choosing a type of non-printable dummy features according to an associated maximum intensity that is less than an exposure threshold dose of at least one of the main features;

generating a pattern of the non-printable dummy features according to the target block dummy density ratio R;

generating a modified IC design layout by adding the non-printable dummy features to the IC design layout; and

fabricating an integrated circuit according to the modified IC design layout.

15. The method of claim 14 , wherein the generating the modified IC design layout by adding the non-printable dummy features to the IC design layout comprises adding the non-printable dummy features to a polysilicon design layer included in the IC design layout.

16. The method of claim 14 , wherein the determining the target block dummy density ratio R of the IC design layout according to the optimized block dummy density ratio r 0 includes determining the target block dummy density ratio based on a statistical measure of the total pattern density associated with the subdivisional area.

17. The method of claim 16 , wherein the statistical measure of the total pattern density is based on a standard deviation of an actual block dummy density ratio r.

18. An integrated circuit (IC) fabrication method comprising:

extracting, by a computer processor, an IC design layout presented in one or more data files, the IC design layout including a subdivisional area having a plurality of main features and a plurality of space blocks;

calculating, by the computer processor, an optimized block dummy density ratio r 0 of the IC design layout to obtain an optimized uniformity of pattern density (UPD), the optimized block dummy density ratio r 0 being calculated from a total pattern density associated with the subdivisional area of the IC design layout;

determining a target block dummy density ratio R of the IC design layout according to the optimized block dummy density ratio r 0 and throughput;

choosing a type of sub-resolution dummy features according to an associated maximum intensity that is less than an exposure threshold dose of at least one of the main features;

generating a pattern of the sub-resolution dummy features according to the target block dummy density ratio R;

generating a modified IC design layout by adding the sub-resolution dummy features to a polysilicon design layer included in the IC design layout; and

fabricating an integrated circuit according to the modified IC design layout.

19. The method of claim 18 , wherein the associated maximum intensity is lower than a model threshold by a predetermined margin, wherein the model threshold is based on a simulated critical dimension.

20. The method of claim 18 , wherein the generating the pattern of the sub-resolution dummy features includes generating square type features with size A and configured in an array with a pitch p such that a ratio A 2 /p 2 is equal to the target block dummy density ratio R.