Offset correction circuit and transconductance proportional current generation circuit

1. An offset correction circuit comprising:

an operational amplifier circuit that includes a first amplifier circuit that includes differential pair transistors for amplifying a difference between input voltages and active load transistors connected to the differential pair transistors, and a second amplifier circuit that amplifies an output voltage of the first amplifier circuit;

an offset correction current source that is connected in parallel with the active load transistors and adjusts electric current flowing through the differential pair transistors to correct offset voltage;

an offset correction switch that switches a driving state of the offset correction current source; and

a transconductance proportional current generation circuit that generates a transconductance proportional current for compensating for temperature drift of an offset correction voltage for correcting the offset voltage, the transconductance proportional current being proportional to a transconductance of one or more transistors in the transconductance proportional current generation circuit.

2. The offset correction circuit according to claim 1 , wherein

the transconductance proportional current generation circuit includes:

a current source that flows first electric current whose current value is stable in relation to temperature;

a resistor whose resistance value is stable in relation to temperature;

a first PMOS transistor that includes a gate and a drain connected to the resistor, wherein the first electric current flows through the first PMOS transistor;

a second PMOS transistor that includes a common gate with the first PMOS transistor, wherein the first electric current flows through the second PMOS transistor;

a first NMOS transistor that includes a gate and a drain connected to a drain of the second PMOS transistor and a source that is grounded;

a second NMOS transistor that includes a common gate with the first NMOS transistor and a source that is grounded, wherein the first electric current flows through the second NMOS transistor;

a third PMOS transistor that includes a gate that receives voltage that is lower than gate voltage of the first PMOS transistor by dropping voltage of the resistor, wherein second electric current flows through the third PMOS transistor; and

a third NMOS transistor that is diode-connected, wherein the first electric current in the second electric current flows through the second NMOS transistor, and the transconductance proportional current obtained by subtracting the first electric current from the second electric current flows through the third NMOS transistor,

wherein the transconductance proportional current is proportional to a transconductance of the third PMOS transistor and flows through a device including a common gate with the third NMOS transistor.

3. The offset correction circuit according to claim 2 , wherein

a source of the first PMOS transistor is connected to a power supply, a source of the second PMOS transistor, and a source of the third PMOS transistor,

the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor, and one end of the resistor,

another end of the resistor is connected to an input terminal of the current source and the gate of the third PMOS transistor,

the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor,

a drain of the third PMOS transistor is connected to a drain of the second NMOS transistor, a drain of the third NMOS transistor, a gate of the third NMOS transistor, and an output terminal of the transconductance proportional current generation circuit, and

an output terminal of the current source and sources of the first, second, and third NMOS transistors are connected to a ground.

4. The offset correction circuit according to claim 1 , wherein

the offset correction current source includes a plurality of current sources whose electric current amounts are weighted, and variably sets electric current to flow by switching of the offset correction switch.

5. The offset correction circuit according to claim 2 , further comprising:

a fourth PMOS transistor that is provided between the drain of the second PMOS transistor and the gate and the drain of the first NMOS transistor and includes a source connected to the drain of the second PMOS transistor and a drain connected to the gate and the drain of the first NMOS transistor, wherein the first electric current flows through the fourth PMOS transistor;

a fifth PMOS transistor that includes a source connected to a drain of the third PMOS transistor and a gate connected to a gate of the fourth PMOS transistor, wherein the second electric current flows through the fifth PMOS transistor; and

a sixth PMOS transistor that includes a source connected to the gate of the third PMOS transistor and a gate and a drain connected to the gate of the fourth PMOS transistor, wherein the first electric current flows through the sixth PMOS transistor.

6. A transconductance proportional current generation circuit for generating electric current proportional to transconductance, comprising:

a current source that flows first electric current whose current value is stable in relation to temperature;

a resistor whose resistance value is stable in relation to temperature;

a first PMOS transistor that includes a gate and a drain connected to the resistor, wherein the first electric current flows through the first PMOS transistor;

a second PMOS transistor that includes a common gate with the first PMOS transistor, wherein the first electric current flows through the second PMOS transistor;

a first NMOS transistor that includes a gate and a drain connected to a drain of the second PMOS transistor and a source that is grounded;

a second NMOS transistor that includes a common gate with the first NMOS transistor and a source that is grounded, wherein the first electric current flows through the second NMOS transistor;

a third PMOS transistor that includes a gate that receives voltage that is lower than gate voltage of the first PMOS transistor by dropping voltage of the resistor, wherein second electric current flows through the third PMOS transistor; and

a third NMOS transistor that is diode-connected, wherein transconductance proportional current obtained by subtracting the first electric current from the second electric current flows through the third NMOS transistor,

wherein the transconductance proportional current proportional to transconductance of the third PMOS transistor flows through a device including a common gate with the third NMOS transistor.

7. The transconductance proportional current generation circuit according to claim 6 , wherein

a source of the first PMOS transistor is connected to a power supply, a source of the second PMOS transistor, and a source of the third PMOS transistor,

the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor, and one end of the resistor,

another end of the resistor is connected to an input terminal of the current source and the gate of the third PMOS transistor,

the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor,

a drain of the third PMOS transistor is connected to a drain of the second NMOS transistor, a drain of the third NMOS transistor, a gate of the third NMOS transistor, and an output terminal of the transconductance proportional current generation circuit, and

an output terminal of the current source and sources of the first, second, and third NMOS transistors are connected to a ground.

8. The transconductance proportional current generation circuit according to claim 6 , further comprising:

a fourth PMOS transistor that is provided between the drain of the second PMOS transistor and the gate and the drain of the first NMOS transistor and includes a source connected to the drain of the second PMOS transistor and a drain connected to the gate and the drain of the first NMOS transistor, wherein the first electric current flows through the fourth PMOS transistor;

a fifth PMOS transistor that includes a source connected to a drain of the third PMOS transistor and a gate connected to a gate of the fourth PMOS transistor, wherein the second electric current flows through the fifth PMOS transistor; and

a sixth PMOS transistor that includes a source connected to the gate of the third PMOS transistor and a gate and a drain connected to the gate of the fourth PMOS transistor, wherein the first electric current flows through the sixth PMOS transistor.