Semiconductor device

1. A semiconductor device, comprising:

a substrate;

a lower electrode structure above the substrate and extending in a direction crossing an upper surface of the substrate;

a dielectric layer on side surfaces and an upper surface of the lower electrode structure; and

an upper electrode structure on the dielectric layer, wherein the lower electrode structure, the dielectric layer, and the upper electrode structure form a capacitor, and wherein the lower electrode structure includes:

a first lower electrode pattern having a hollow shape;

a barrier layer accommodated in the first lower electrode pattern; and

a second lower electrode pattern in a space defined by the barrier layer, wherein

a first sheet resistance of the first lower electrode pattern is equal to or greater than two times of a second sheet resistance of the second lower electrode pattern.

2. The semiconductor device as claimed in claim 1 , wherein:

the first lower electrode pattern of the lower electrode structure entirely covers a bottom surface of the barrier layer of the lower electrode structure, and

a width of the second lower electrode pattern is greater than a thickness of the first lower electrode pattern.

3. The semiconductor device as claimed in claim 1 , wherein the barrier layer includes metal silicon nitride.

4. The semiconductor device as claimed in claim 3 , wherein the barrier layer includes TiSiN.

5. The semiconductor device as claimed in claim 3 , wherein a silicon concentration in the barrier layer decreases in a direction from a first interface between the first lower electrode pattern and the barrier layer to a second interface between the barrier layer and the second lower electrode pattern.

6. The semiconductor device as claimed in claim 3 , wherein:

the barrier layer has a multilayer structure including a lower barrier layer and an upper barrier layer that are stacked, and

a silicon concentration of the upper barrier layer is less than that of the lower barrier layer.

7. The semiconductor device as claimed in claim 1 , wherein the barrier layer has a multilayer structure including a metal nitride layer and a silicon nitride layer are stacked alternately at least once.

8. The semiconductor device as claimed in claim 7 , wherein:

the barrier layer includes a first metal nitride layer, a first silicon nitride layer, a second metal nitride layer, a second silicon nitride layer, and a third metal nitride layer stacked on the first lower electrode pattern in the stated order,

a first thickness of the first metal nitride layer is less than a second thickness of the second metal nitride layer, and

the second thickness is less than a third thickness of the third metal nitride layer.

9. The semiconductor device as claimed in claim 1 , wherein:

a top surface of the first lower electrode pattern, a top surface of the barrier layer, and a top surface of the second lower electrode pattern are at a same level as one another, and

the dielectric layer covers the top surface of the first lower electrode pattern, the top surface of the barrier layer, and the top surface of the second lower electrode pattern.

10. The semiconductor device as claimed in claim 1 , wherein the second lower electrode pattern includes:

a first portion filling an internal space defined by the barrier layer; and

a second portion covering a top surface of the first lower electrode pattern and a top surface of the barrier layer.

11. The semiconductor device as claimed in claim 10 , wherein:

the first lower electrode pattern and the barrier layer have U-shaped cross-sections, and

the second lower electrode pattern has a T-shaped cross-section.

12. The semiconductor device as claimed in claim 10 , wherein the dielectric layer abuts side surfaces of the first lower electrode pattern and side surfaces and a top surface of the second portion of the second lower electrode pattern and does not abut the barrier layer.

13. The semiconductor device as claimed in claim 1 , wherein a width of the second lower electrode pattern is about 40 Å or greater.

14. A semiconductor device, comprising:

a substrate;

contact plugs in an interlayer insulation pattern layer on the substrate;

lower electrode structures above the substrate, abutting respective ones of the contact plugs, and extending in a direction crossing an upper surface of the substrate;

supports connecting adjacent lower electrode structures, from among the lower electrode structures, to each other;

a dielectric layer along external surfaces of the lower electrode structures and the supports; and

an upper electrode structure on the dielectric layer, wherein the lower electrode structures, the dielectric layer, and the upper electrode structure form a capacitor, and wherein each of the lower electrode structures includes:

a first lower electrode pattern having a cylindrical shape;

a barrier layer on the first lower electrode pattern; and

a second lower electrode pattern in a space defined by the barrier layer.

15. A capacitor, comprising:

a lower electrode structure;

an upper electrode structure; and

a dielectric layer between the lower and upper electrode structures, wherein the lower electrode structure includes a first electrode pattern, a second electrode pattern, and a barrier layer, the barrier layer between the first electrode pattern and the second electrode pattern in a space defined by the barrier layer, wherein:

the first electrode pattern of the lower electrode structure has a hollow shape, and accommodates the barrier layer and the second electrode pattern of the lower electrode structure therein, and wherein

a first sheet resistance of the first electrode pattern of the lower electrode structure is equal to or greater than two times of a second sheet resistance of the second electrode pattern of the lower electrode structure.

16. The capacitor as claimed in claim 15 , wherein

the first electrode pattern of the lower electrode structure entirely covers a bottom surface of the barrier layer of the lower electrode structure.

17. The capacitor as claimed in claim 15 , wherein the barrier layer includes metal silicon nitride.

18. The capacitor as claimed in claim 15 , wherein the first electrode pattern has a thickness less than a width of the second electrode pattern.

19. The capacitor as claimed in claim 15 , wherein:

the barrier layer includes a silicon concentration that decreases from a first interface between the first electrode pattern and the barrier layer to a second interface between the barrier layer and the second electrode pattern.