Efficient signaling scheme for high-speed ultra short reach interfaces

1. A packaged semiconductor device, comprising:

a substrate;

a first integrated circuit (IC) chip mounted on the substrate to receive first data and including a first transfer interface to transmit the first data via first conductors formed in the substrate;

a second IC chip mounted on the substrate in a collinear planar arrangement with the first IC chip and having a second transfer interface to receive the first data, the second IC including on-chip conductors to route the first data on-chip to an output interface, the output interface to transmit the first data via second conductors formed on the substrate;

a third IC chip mounted on the substrate in a collinear planar arrangement with the first IC chip and the second IC chip and having a third transfer interface to receive the first data via the second conductors; and

wherein the second IC chip is disposed between the first IC chip and the third IC chip.

2. The packaged semiconductor device according to claim 1 , wherein:

each IC chip comprises an Ethernet transceiver chip that includes an Ethernet port.

3. The packaged semiconductor device according to claim 2 , further comprising:

serial interface circuitry configured for connecting to less than all of the first, second and third IC chips.

4. The packaged semiconductor device according to claim 3 , wherein:

the IC chips are configured to transfer the first data between the multiple Ethernet ports and the serial interface circuitry.

5. The packaged semiconductor device according to claim 1 , wherein:

the second IC chip is configured as a repeater.

6. The packaged semiconductor device according to claim 5 , wherein:

the substrate does not include conductors for routing the second data underneath the second IC chip.

7. The packaged semiconductor device according to claim 1 , wherein:

the first IC chip is configured as a master IC chip and provides a source synchronous timing signal; and

the second IC chip is configured as a slave IC chip and receives the source synchronous timing signal from the master IC chip.

8. A method of operation in a multi-chip module (MCM), the method comprising:

transmitting first data via a first output interface of a first integrated circuit (IC) chip along first conductors formed in the substrate;

receiving the first data with a second transfer interface of a second IC chip mounted on the substrate in a collinear planar arrangement with the first IC chip;

routing the first data on-chip to an output interface of the second IC chip;

transmitting the first data via the output interface of the second IC chip along second conductors formed on the substrate; and

receiving the first data with a third transfer interface of a third IC chip via the second conductors, the third IC chip mounted on the substrate in a collinear planar arrangement with the first IC chip and the second IC chip and disposed between the first IC chip and the second IC chip.

9. The method according to claim 8 , wherein:

the first data comprises Ethernet data received via a line side of an Ethernet link.

10. The method according to claim 8 , further comprising:

after receiving the first data, serializing the first data with serial interface circuitry disposed on the third IC chip.

11. The method according to claim 8 , wherein routing the first data on-chip comprises:

repeating the first data received from the first IC chip to the third IC chip without routing the first data along substrate conductors under the second IC chip.