WIDE BANDGAP SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR CELLS AND COMPENSATION STRUCTURE
A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.
1 . A semiconductor device comprising:
transistor cells formed in a semiconductor portion from a wide bandgap material and electrically connected to a gate terminal, a source terminal and a drain terminal;
a compensation structure electrically connected with the gate terminal and at least one of the source terminal and the drain terminal, wherein an effective capacitance of the compensation structure has a temperature coefficient at least partly compensating for a temperature coefficient of a ratio between a gate-to-drain capacitance and a gate-to-source capacitance of the transistor cells.
2 . The semiconductor device of claim 1 , wherein
the compensation structure comprises a first capacitive structure with a first capacitance effective between the drain terminal and the gate terminal and wherein the first capacitance has a negative temperature coefficient.
3 . The semiconductor device of claim 1 , wherein
the compensation structure includes a second capacitive structure with a capacitance effective between the gate terminal and the source terminal and wherein the capacitance has a positive temperature coefficient.
4 . The semiconductor device of claim 1 , wherein
the compensation structure comprises a series connection of a first capacitive structure and a second capacitive structure between the gate terminal and the drain terminal, and a thermistor structure with a negative temperature coefficient between the source terminal and a connection node between the first and second capacitive structures.
5 . The semiconductor device of claim 4 , wherein
the thermistor structure comprises a doped region in the semiconductor portion.
6 . The semiconductor device of claim 5 , wherein
the doped region contains aluminum at a concentration of at least 5E17 cm 3 .
7 . The semiconductor device of claim 5 , further comprising:
a contact structure extending through an interlayer dielectric and electrically connecting a source electrode with the doped region, wherein the interlayer dielectric separates the source electrode and the semiconductor portion.
8 . The semiconductor device of claim 5 , wherein
a first electrode of the first capacitive structure is a portion of a gate metallization separated from the semiconductor portion by a portion of an interlayer dielectric.
9 . The semiconductor device of claim 8 , wherein
a gate pad forms the first electrode of the first capacitive structure.
10 . The semiconductor device of claim 5 , wherein
the doped region forms a second electrode of the first capacitive structure, the connection node and a first electrode of the second capacitive structure.
11 . The semiconductor device of claim 5 , further comprising:
a drain structure in the semiconductor portion, the drain structure electrically connecting the transistor cells with a drain electrode, the drain structure forming a pn junction with the doped region and forming a second electrode of the second capacitive structure.
12 . A semiconductor device comprising:
transistor cells in a semiconductor portion from silicon carbide, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode;
a doped region in the semiconductor portion, wherein the doped region is electrically connected to the source electrode and a resistance of the doped region has a negative temperature coefficient;
an interlayer dielectric separating the gate metallization from the doped region;
a drain structure in the semiconductor portion, wherein the drain structure electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.
13 . The semiconductor device of claim 12 , wherein
the doped region contains aluminum at a concentration of at least 5E17 cm −3 .
14 . The semiconductor device of claim 12 , further comprising:
a contact structure extending through the interlayer dielectric and directly adjoining to the source electrode and the doped region.
15 . The semiconductor device of claim 14 , wherein
two of the contact structures are arranged at opposite sides of the gate metallization.
16 . The semiconductor device of claim 12 , wherein
the gate metallization comprises a gate pad.
17 . The semiconductor device of claim 12 , wherein
the doped region has a minimum active horizontal extension of at least 100 μm.
18 . The semiconductor device of claim 12 , wherein
the doped region directly adjoins to a first surface of the semiconductor portion.
19 . The semiconductor device of claim 12 , wherein
the drain structure includes a heavily doped contact layer and a lightly doped drift zone forming the pn junction with the doped region and separating the doped region from the contact layer.
20 . A semiconductor device comprising:
transistor cells in a semiconductor portion from silicon carbide, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode;
a doped region in the semiconductor portion, wherein the doped region is electrically connected to the source electrode and a resistance of the doped region has a negative temperature coefficient;
an interlayer dielectric separating the gate metallization from the doped region;
a drain structure in the semiconductor portion, wherein the drain structure electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region;
a contact structure extending through the interlayer dielectric and directly adjoining to the source electrode and the doped region;
the doped region directly adjoins to a first surface of the semiconductor portion; and
the drain structure includes a heavily doped contact layer and a lightly doped drift zone forming the pn junction with the doped region and separating the doped region from the contact layer.