Continuous time linear equalizer with two adaptive zero frequency locations
The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.
1. A continuous-time linear equalizer device comprising:
a first input terminal;
a second input terminal;
a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal;
a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal;
a first source resistor coupled to the first source terminal;
a second source resistor coupled to the first source resistor and the second source terminal;
a first terminal positioned between the first source resistor and the second source resistor;
a first source capacitor coupled to the first source terminal;
a second source capacitor coupled to the second source terminal;
a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal;
a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero; and
a first gain tuning circuit coupled to the first compensation circuit.
2. The device of claim 1 wherein the first input terminal and the second input terminal receive a pair of differential input signals.
3. The device of claim 1 wherein the first source resistor and the first source capacitor are configured in parallel.
4. The device of claim 1 further comprising a bias current source coupled to the first source terminal.
5. The device of claim 1 wherein the first resistor comprises a variable resistor.
6. The device of claim 1 wherein the first resistor and the first capacitor is associated with a predetermined high-frequency zero.
7. The device of claim 1 wherein the first gain tuning circuit comprises a first switch, the first switch being coupled to a control logic.
8. The device of claim 1 further comprising a pair of common mode resistors coupled to the first drain terminal.
9. The device of claim 1 wherein the first input transistor comprises an NMOS transistor.
10. The device of claim 1 wherein the first capacitor comprises a variable capacitor.
11. The device of claim 1 wherein the first load resistor comprises a variable resistor.
12. The device of claim 11 further comprising:
a second compensation circuit coupled to the second drain terminal, the second compensation circuit comprising a second load capacitor and a second load resistor, the second load capacitor and the second load resistor being associated with the predetermined low-frequency zero;
a second gain tuning circuit coupled to the second compensation circuit.
13. The device of claim 12 further comprising:
a first common mode resistor coupled to the first drain terminal;
a second common mode resistor coupled to the second drain terminal, the second common mode resistor being characterized by a resistance value matching the first common mode resistor;
an operational amplifier coupled to the first common mode resistor and the second common mode resistor.
14. The device of claim 13 further comprising:
a first common transistor comprising a third gate terminal and a third source terminal and a third drain terminal, the third gate terminal being coupled to an output of the operation amplifier, the third terminal being coupled to the first compensation circuit;
a second common transistor comprising a fourth gate terminal and a fourth source terminal and a fourth drain terminal, the fourth gate terminal being coupled to the output of the operational amplifier.
15. The device of claim 14 further comprising a supply voltage coupled to the first load capacitor.
16. A continuous-time linear equalizer device comprising:
a first input terminal;
a second input terminal;
a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal;
a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal;
a first source resistor coupled to the first source terminal;
a second source resistor coupled to the first source resistor and the second source terminal;
a first terminal positioned between the first source resistor and the second source resistor;
a first source capacitor coupled to the first source terminal;
a second source capacitor coupled to the second source terminal;
a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal;
a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero.
17. The apparatus of claim 16 further comprising:
a second compensation circuit coupled to the second drain terminal;
a first gain tuning circuit coupled to the first compensation circuit;
a second gain tuning circuit coupled to the second compensation circuit;
a common mode operational amplifier coupled to the second compensation circuit.
18. A continuous-time linear equalizer device comprising:
a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to a first input signal;
a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to a second input signal;
a first source resistor coupled to the first source terminal;
a second source resistor coupled to the first source resistor and the second source terminal;
a first terminal positioned between the first source resistor and the second source resistor;
a first source capacitor coupled to the first source terminal;
a second source capacitor coupled to the second source terminal;
a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal;
a first compensation circuit coupled to the first drain terminal, the first compensation circuit comprising a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero; and
a second compensation circuit coupled to the second source terminal.
19. The device of claim 18 further comprising:
a first gain tuning circuit coupled to the first compensation circuit;
a second gain tuning circuit coupled to the second compensation circuit;
a common mode operational amplifier coupled to the second compensation circuit.