Continuous time linear equalizer and device including the same
A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.
1 . A device comprising:
a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path,
wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path in a test mode, and equalize a first data signal in a normal mode, equalizing the first data signal including removing an offset from the first data signal using the calibration current path, and
wherein the path includes a plurality of first transistors, and each first transistor of the plurality of first transistors is configured to,
receive internal test data through a respective gate terminal of the first transistor in the test mode, and
receive offset data through the respective gate terminal of the first transistor in the normal mode.
2 . The device of claim 1 , wherein the receiver analog front-end circuit is further configured to selectively transmit one of the internal test data or the offset data to the plurality of first transistors based on a mode selection signal.
3 . The device of claim 1 , wherein the receiver analog front-end circuit further includes:
a continuous time linear equalizer (CTLE); and
the path is included in the CTLE, and
the CTLE is configured to output the first data signal.
4 . The device of claim 3 , wherein the CTLE includes:
a high-frequency filter circuit;
a fixed gain amplifier circuit configured to receive a plurality of first inputs from the high-frequency filter circuit; and
a variable gain amplifier circuit configured to receive a plurality of second inputs from the fixed gain amplifier circuit,
wherein the path is included in the fixed gain amplifier circuit, and
the variable gain amplifier circuit is further configured to output the first data signal.
5 . The device of claim 4 , wherein the high-frequency filter circuit is configured to be deactivated in response to the receiver analog front-end circuit being in the test mode, and to be activated in response to the receiver analog front-end circuit being in the normal mode.
6 . The device of claim 4 , wherein the fixed gain amplifier circuit includes:
a first current source configured to amplify the plurality of first inputs and output a first current;
a second current source configured to remove the offset from the output of the CTLE and output a second current; and
a plurality of second transistors,
wherein each of the plurality of second transistors is configured to be turned on based on the receiver analog front-end circuit being in the test mode and turned off based on the receiver analog front-end circuit being in the normal mode,
wherein the receiver analog front-end circuit is further configured to sum the first current and the second current and transmit results of the summing through the path in the test mode, and transmit only the second current through the path in the normal mode.
7 . The device of claim 6 , wherein the receiver analog front-end circuit is further configured to:
transmit the first current and the second current through the internal loopback current path in the test mode; and
transmit the second current through the calibration current path in the normal mode.
8 . The device of claim 1 , further comprising:
a serializer/deserializer (SERDES) circuit configured to parallelize the equalized first data signal received from the receiver analog front-end circuit, or serialize and transmit a second data signal to a transmitter driver circuit, and
wherein the internal loopback current path is included in the SERDES circuit and the receiver analog front-end circuit.
9 . The device of claim 1 , further comprising a controller configured to control the receiver analog front-end circuit to operate in one of the test mode or the normal mode.
10 . The device of claim 1 , further comprising:
a transmitter driver circuit configured to transmit a second data signal to an external destination based on the receive analog front-end circuit being in the normal mode, and is configured to be deactivated based on the receiver analog front-end circuit being in the test mode.
11 . A device comprising:
a receiver analog front-end circuit configured to equalize a first data signal;
a transmitter driver circuit configured to transmit a second data signal to an external destination;
a serializer/deserializer (SERDES) circuit configured to parallelize the equalized first data signal provided from the receiver analog front-end circuit, or serialize and provide the second data signal to the transmitter driver circuit; and
a controller configured to control the receiver analog front-end circuit and the SERDES circuit to enable one of an internal loopback current path or a calibration current path,
wherein
the receiver analog front-end circuit is further configured to use the internal loopback current path to test the receiver analog front-end circuit and the SERDES circuit in a test mode, and use the calibration current path to equalize the first data signal by removing an offset from the first data signal in a normal mode,
wherein the receiver analog front-end circuit includes a plurality of first transistors corresponding to a path shared between the internal loopback current path and the calibration current path, and
wherein each first transistor of the plurality of first transistors is configured to,
receive internal test data through a respective gate terminal of the first transistor in the test mode, and
receive offset data through the respective gate terminal of the first transistor in the normal mode.
12 . The device of claim 11 , wherein the controller is further configured to:
control transmission of the offset data to the gate terminal of each first transistor of the plurality of first transistors based on the receiver analog front-end circuit being in the test mode; and
control transmission of the internal test data to the gate terminal of each first transistor of the plurality of first transistors based on the receiver analog front-end circuit being in the normal mode.
13 . The device of claim 12 , wherein
the controller is further configured to provide a mode selection signal to the receiver analog front-end circuit; and
the receiver analog front-end circuit is further configured to selectively provide one of the internal test data or the offset data to the gate terminal of each first transistor of the plurality of first transistors based on the mode selection signal.
14 . The device of claim 13 , wherein the receiver analog front-end circuit further includes:
a third transistor configured to receive the mode selection signal through a gate terminal of the third transistor, and selectively output the internal test data in response to the mode selection signal; and
a fourth transistor configured to receive an inverted signal of the mode selection signal through a gate terminal of the third transistor, and selectively output the offset data in response to the inverted signal.
15 . The device of claim 11 , wherein the receiver analog front-end circuit further includes:
a continuous time linear equalizer (CTLE), the CTLE including the plurality of first transistors, and
the CTLE is configured to output the first data signal as a positive output signal and a negative output signal.
16 . The device of claim 15 , wherein the CTLE includes:
a first current source configured to output a first current;
a second current source configured to output a second current; and
a plurality of second transistors,
wherein the controller is further configured to,
generate a mode selection signal at a first voltage level, and transmit the mode selection signal to a gate terminal of each second transistor of the plurality of second transistors based on the receiver analog front-end circuit being in the test mode, the mode selection signal at the first voltage level turning on the plurality of second transistors, and
generate the mode selection signal at a second voltage level, and transmit the mode selection signal to the gate terminal of each second transistor of the plurality of second transistors, the mode selection signal at the second voltage level turning off the plurality of second transistors, and
wherein the receiver analog front-end circuit is further configured to receive the first current and the second current through the path in the test mode, and receive only the second current through the path in the normal mode.
17 . A continuous time linear equalizer (CTLE) comprising:
a high-frequency filter circuit configured to receive a first positive input and a first negative input, and output a positive selection input and a negative selection input based on the first positive input and the first negative input;
a fixed gain amplifier circuit configured to receive a second positive input, a second negative input, the positive selection input, and the negative selection input from the high-frequency filter circuit; and
a variable gain amplifier circuit configured to receive a third positive input and a third negative input from the fixed gain amplifier circuit,
wherein the fixed gain amplifier circuit includes:
a first current source configured to amplify the second positive input or the second negative input;
a second current source configured to remove an offset from the third positive input and the third negative input;
a plurality of first transistors configured to form a first path from the first current source in response to the second positive input or the second negative input;
a plurality of second transistors configured to form a second path from the second current source in response to the positive selection input or the negative selection input; and
a plurality of third transistors configured to generate a third path from the first current source in response to a mode selection signal, and
wherein the positive selection input and the negative selection input correspond to internal test data based on the CTLE being in a test mode and correspond to offset data based on the CTLE being in a normal mode.
18 . The CTLE of claim 17 , wherein
the first transistors are configured to be turned off based on the CTLE being in the test mode;
the second and third transistors are configured to be turned on based on the CTLE being in the test mode;
an internal loopback current path including the second and third paths is enabled based on the CTLE being in the test mode;
the third transistors are configured to be turned off based on the CTLE being in the normal mode;
the first and second transistors are configured to be turned on based on the CTLE being in the normal mode; and
a calibration current path including the first and second paths is enabled based on the CTLE being in the normal mode.
19 . The CTLE of claim 17 , wherein the high-frequency filter circuit includes a plurality of fourth transistors each configured to receive the first positive input or the first negative input through a respective gate terminal, and
in response to the CTLE being in the test mode, the plurality of fourth transistors are configured to turn off based on values of the first positive input and the first negative input.